2018-01-05 02:19:51 -04:00
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#!/usr/bin/env python
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import sys, fnmatch
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import importlib
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# peripheral types that can be shared, wildcard patterns
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2020-10-12 16:57:29 -03:00
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SHARED_MAP = ["I2C*", "USART*_TX", "UART*_TX", "SPI*", "TIM*_UP", "TIM*_CH*"]
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2018-01-05 02:19:51 -04:00
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ignore_list = []
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dma_map = None
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debug = False
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2021-03-01 17:52:11 -04:00
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def check_possibility(periph, dma_stream, curr_dict, dma_map, check_list, cannot_use_stream, forbidden_map):
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2019-02-14 06:18:13 -04:00
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global ignore_list
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2021-01-17 12:10:59 -04:00
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if debug:
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print('............ Checking ', periph, dma_stream, 'without', cannot_use_stream)
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2020-10-07 18:46:48 -03:00
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for other_periph in sorted(curr_dict.keys()):
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2018-01-30 01:24:13 -04:00
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if other_periph != periph:
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if curr_dict[other_periph] == dma_stream:
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2021-03-01 17:52:11 -04:00
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if other_periph in forbidden_map[periph]:
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if debug:
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print('.................... Forbidden', periph, other_periph)
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return False
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2021-01-17 12:10:59 -04:00
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if debug:
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print('.................... Collision', other_periph, dma_stream)
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2018-01-30 01:24:13 -04:00
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ignore_list.append(periph)
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check_str = "%s(%d,%d) %s(%d,%d)" % (
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other_periph, curr_dict[other_periph][0],
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curr_dict[other_periph][1], periph, dma_stream[0],
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dma_stream[1])
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#check if we did this before
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if check_str in check_list:
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return False
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check_list.append(check_str)
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if debug:
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print("Trying to Resolve Conflict: ", check_str)
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#check if we can resolve by swapping with other periphs
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2018-03-13 21:28:14 -03:00
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for streamchan in dma_map[other_periph]:
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stream = (streamchan[0], streamchan[1])
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2021-01-17 12:10:59 -04:00
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if stream != curr_dict[other_periph] and \
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stream not in cannot_use_stream and \
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2021-03-01 17:52:11 -04:00
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check_possibility(other_periph, stream, curr_dict, dma_map, check_list,
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cannot_use_stream+[(dma_stream)], forbidden_map):
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2021-01-17 12:10:59 -04:00
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curr_dict[other_periph] = stream
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if debug:
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print ('....................... Resolving', other_periph, stream)
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2018-01-30 01:24:13 -04:00
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return True
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2021-01-17 12:10:59 -04:00
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if debug:
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print ('....................... UnSolved !!!!!!!!', periph, dma_stream)
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2018-01-30 01:24:13 -04:00
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return False
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2021-01-17 12:10:59 -04:00
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if debug:
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print ('....................... Solved ..........', periph, dma_stream)
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2018-01-30 01:24:13 -04:00
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return True
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2018-02-08 07:13:00 -04:00
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def can_share(periph, noshare_list):
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2018-01-30 01:24:13 -04:00
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'''check if a peripheral is in the SHARED_MAP list'''
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2018-02-08 07:13:00 -04:00
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for noshare in noshare_list:
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if fnmatch.fnmatch(periph, noshare):
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return False
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2018-01-30 01:24:13 -04:00
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for f in SHARED_MAP:
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if fnmatch.fnmatch(periph, f):
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return True
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if debug:
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print("%s can't share" % periph)
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return False
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2018-01-05 02:19:51 -04:00
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2019-02-19 22:55:18 -04:00
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# list of peripherals on H7 that are on DMAMUX2 and BDMA
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have_DMAMUX = False
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DMAMUX2_peripherals = [ 'I2C4', 'SPI6', 'ADC3' ]
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def dmamux_channel(key):
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'''return DMAMUX channel for H7'''
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for p in DMAMUX2_peripherals:
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if key.find(p) != -1:
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return 'STM32_DMAMUX2_' + key
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# default to DMAMUX1
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return 'STM32_DMAMUX1_' + key
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def dma_name(key):
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'''return 'DMA' or 'BDMA' based on peripheral name'''
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if not have_DMAMUX:
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return "DMA"
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for p in DMAMUX2_peripherals:
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if key.find(p) != -1:
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return 'BDMA'
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return 'DMA'
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2018-01-05 02:19:51 -04:00
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def chibios_dma_define_name(key):
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2018-01-30 01:24:13 -04:00
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'''return define name needed for board.h for ChibiOS'''
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2019-02-19 22:55:18 -04:00
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dma_key = key + '_' + dma_name(key)
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2018-01-30 01:24:13 -04:00
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if key.startswith('ADC'):
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2019-02-19 22:55:18 -04:00
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return 'STM32_ADC_%s_' % dma_key
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2018-01-30 01:24:13 -04:00
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elif key.startswith('SPI'):
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2019-02-19 22:55:18 -04:00
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return 'STM32_SPI_%s_' % dma_key
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2018-01-30 01:24:13 -04:00
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elif key.startswith('I2C'):
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2019-02-19 22:55:18 -04:00
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return 'STM32_I2C_%s_' % dma_key
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2018-01-30 01:24:13 -04:00
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elif key.startswith('USART'):
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2019-02-19 22:55:18 -04:00
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return 'STM32_UART_%s_' % dma_key
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2018-01-30 01:24:13 -04:00
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elif key.startswith('UART'):
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2019-02-19 22:55:18 -04:00
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return 'STM32_UART_%s_' % dma_key
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2018-03-02 22:57:33 -04:00
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elif key.startswith('SDIO') or key.startswith('SDMMC'):
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2019-02-19 22:55:18 -04:00
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return 'STM32_SDC_%s_' % dma_key
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2018-01-30 01:24:13 -04:00
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elif key.startswith('TIM'):
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2019-02-19 22:55:18 -04:00
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return 'STM32_TIM_%s_' % dma_key
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2018-01-30 01:24:13 -04:00
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else:
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print("Error: Unknown key type %s" % key)
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sys.exit(1)
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2018-01-05 02:19:51 -04:00
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2018-02-08 07:13:00 -04:00
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def get_list_index(peripheral, priority_list):
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'''return index into priority_list for a peripheral'''
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for i in range(len(priority_list)):
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str = priority_list[i]
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if fnmatch.fnmatch(peripheral, str):
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return i
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# default to max priority
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return len(priority_list)
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def get_sharing_priority(periph_list, priority_list):
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'''get priority of a list of peripherals we could share with'''
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highest = len(priority_list)
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for p in periph_list:
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prio = get_list_index(p, priority_list)
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if prio < highest:
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highest = prio
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return highest
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2021-03-07 23:24:38 -04:00
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def generate_DMAMUX_map_mask(peripheral_list, channel_mask, noshare_list, dma_exclude, stream_ofs):
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2019-02-14 06:18:13 -04:00
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'''
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generate a dma map suitable for a board with a DMAMUX
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In principle any peripheral can use any stream, but we need to
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ensure that a peripheral doesn't try to use the same stream as its
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partner (eg. a RX/TX pair)
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'''
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dma_map = {}
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idsets = {}
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# first unshareable peripherals
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2019-02-19 22:55:18 -04:00
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available = channel_mask
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2019-02-14 06:18:13 -04:00
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for p in peripheral_list:
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dma_map[p] = []
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idsets[p] = set()
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for p in peripheral_list:
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2019-02-18 18:50:04 -04:00
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if can_share(p, noshare_list) or p in dma_exclude:
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2019-02-14 06:18:13 -04:00
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continue
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for i in range(16):
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mask = (1<<i)
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if available & mask != 0:
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2019-02-18 18:50:04 -04:00
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available &= ~mask
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2019-02-14 06:18:13 -04:00
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dma = (i // 8) + 1
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stream = i % 8
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2021-03-07 23:24:38 -04:00
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dma_map[p].append((dma,stream))
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2019-02-14 06:18:13 -04:00
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idsets[p].add(i)
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break
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2019-02-18 18:50:04 -04:00
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if debug:
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print('dma_map1: ', dma_map)
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2019-03-02 05:21:36 -04:00
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print('available: 0x%04x' % available)
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2019-02-18 18:50:04 -04:00
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2019-02-14 06:18:13 -04:00
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# now shareable
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idx = 0
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for p in peripheral_list:
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2019-02-18 18:50:04 -04:00
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if not can_share(p, noshare_list) or p in dma_exclude:
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2019-02-14 06:18:13 -04:00
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continue
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base = idx % 16
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for i in range(16):
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found = None
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2019-04-19 22:22:06 -03:00
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for ii in list(range(base,16)) + list(range(0,base)):
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2019-02-14 06:18:13 -04:00
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if (1<<ii) & available == 0:
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continue
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dma = (ii // 8) + 1
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stream = ii % 8
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if (dma,stream) in dma_map[p]:
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2021-03-01 17:52:11 -04:00
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# this peripheral is already using the stream
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2019-02-14 06:18:13 -04:00
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continue
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# prevent attempts to share with other half of same peripheral
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if p.endswith('RX'):
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2020-12-30 08:08:16 -04:00
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other = p[:-2] + 'TX'
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2019-02-14 06:18:13 -04:00
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elif p.endswith('TX'):
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2020-12-30 08:08:16 -04:00
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other = p[:-2] + 'RX'
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else:
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other = None
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2019-02-14 06:18:13 -04:00
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2021-03-11 19:30:17 -04:00
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if other is not None and other in idsets and ii in idsets[other]:
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2020-12-30 08:08:16 -04:00
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if len(idsets[p]) >= len(idsets[other]) and len(idsets[other]) > 0:
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2020-10-12 16:57:29 -03:00
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continue
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2020-12-30 08:08:16 -04:00
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idsets[other].remove(ii)
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dma_map[other].remove((dma,stream))
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2019-02-14 06:18:13 -04:00
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found = ii
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break
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if found is None:
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continue
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base = (found+1) % 16
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dma = (found // 8) + 1
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stream = found % 8
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dma_map[p].append((dma,stream))
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idsets[p].add(found)
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idx = (idx+1) % 16
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2021-03-07 23:24:38 -04:00
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if stream_ofs != 0:
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# add in stream_ofs to cope with STM32G4
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for p in dma_map.keys():
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for (dma,stream) in dma_map[p]:
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map2 = []
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map2.append((dma,stream+stream_ofs))
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dma_map[p] = map2
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2019-02-14 06:18:13 -04:00
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if debug:
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print('dma_map: ', dma_map)
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print('idsets: ', idsets)
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2019-03-02 05:21:36 -04:00
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print('available: 0x%04x' % available)
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2019-02-14 06:18:13 -04:00
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return dma_map
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2021-03-07 23:24:38 -04:00
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def generate_DMAMUX_map(peripheral_list, noshare_list, dma_exclude, stream_ofs):
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2019-02-19 22:55:18 -04:00
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'''
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generate a dma map suitable for a board with a DMAMUX1 and DMAMUX2
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'''
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# first split peripheral_list into those for DMAMUX1 and those for DMAMUX2
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dmamux1_peripherals = []
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dmamux2_peripherals = []
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for p in peripheral_list:
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if dma_name(p) == 'BDMA':
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dmamux2_peripherals.append(p)
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else:
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dmamux1_peripherals.append(p)
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2021-03-07 23:24:38 -04:00
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map1 = generate_DMAMUX_map_mask(dmamux1_peripherals, 0xFFFF, noshare_list, dma_exclude, stream_ofs)
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2021-08-24 02:18:31 -03:00
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# there are 8 BDMA streams, but an issue has been found where if I2C4 and
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# SPI6 use neighboring streams then we sometimes lose a BDMA completion
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# interrupt. We also found that both ADC3 and SPI6_RX can't use the first
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# stream. To avoid more complications we now statically allocate the BDMA
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# streams for the 3 possible peripherals. To keep this code simpler we
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# still have the mapping code here, but it ends not not being used and the
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# static allocation is in stm32h7_mcuconf.h
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map2 = generate_DMAMUX_map_mask(dmamux2_peripherals, 0xff, noshare_list, dma_exclude, stream_ofs)
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2019-03-02 05:21:36 -04:00
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# translate entries from map2 to "DMA controller 3", which is used for BDMA
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2020-10-07 18:46:48 -03:00
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for p in sorted(map2.keys()):
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2019-03-02 05:21:36 -04:00
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streams = []
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for (controller,stream) in map2[p]:
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streams.append((3,stream))
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map2[p] = streams
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2019-02-19 22:55:18 -04:00
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both = map1
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both.update(map2)
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if debug:
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print('dma_map_both: ', both)
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return both
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2021-03-01 17:52:11 -04:00
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def sharing_allowed(p1, p2):
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'''return true if sharing is allowed between p1 and p2'''
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if p1 == p2:
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return True
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# don't allow RX and TX of same peripheral to share
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if p1.endswith('_RX') and p2.endswith('_TX') and p1[:-2] == p2[:-2]:
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return False
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# don't allow sharing of two TIMn_UP channels as DShot code can't cope
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if p1.endswith("_UP") and p2.endswith("_UP") and p1.startswith("TIM") and p2.startswith("TIM"):
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return False
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return True
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def check_sharing(shared):
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'''check if DMA channel sharing is OK'''
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for p in shared:
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# don't share UART RX with anything
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if (p.startswith("UART") or p.startswith("USART")) and p.endswith("_RX"):
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print("Illegal sharing of %s" % p)
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return False
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# don't share ADC with anything
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if p.startswith("ADC"):
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print("Illegal sharing of %s" % p)
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return False
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for p2 in shared:
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if not sharing_allowed(p, p2):
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print("Illegal sharing of %s and %s" % (p, p2))
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return False
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return True
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def forbidden_list(p, peripheral_list):
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'''given a peripheral, form a list of other peripherals we may not share with'''
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ret = []
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for p2 in peripheral_list:
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if not sharing_allowed(p, p2):
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ret.append(p2)
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return ret
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2018-02-08 07:13:00 -04:00
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def write_dma_header(f, peripheral_list, mcu_type, dma_exclude=[],
|
2021-03-16 04:28:25 -03:00
|
|
|
dma_priority='', dma_noshare=[]):
|
2018-01-30 01:24:13 -04:00
|
|
|
'''write out a DMA resolver header file'''
|
2020-12-30 08:08:16 -04:00
|
|
|
global dma_map, have_DMAMUX, has_bdshot
|
|
|
|
timer_ch_periph = []
|
|
|
|
|
|
|
|
has_bdshot = False
|
2018-02-08 07:13:00 -04:00
|
|
|
|
|
|
|
# form a list of DMA priorities
|
|
|
|
priority_list = dma_priority.split()
|
|
|
|
|
|
|
|
# sort by priority
|
|
|
|
peripheral_list = sorted(peripheral_list, key=lambda x: get_list_index(x, priority_list))
|
|
|
|
|
|
|
|
# form a list of peripherals that can't share
|
2021-03-16 04:28:25 -03:00
|
|
|
noshare_list = dma_noshare[:]
|
2018-02-08 07:13:00 -04:00
|
|
|
|
2018-01-30 01:24:13 -04:00
|
|
|
try:
|
|
|
|
lib = importlib.import_module(mcu_type)
|
2018-08-29 10:18:55 -03:00
|
|
|
if hasattr(lib, "DMA_Map"):
|
|
|
|
dma_map = lib.DMA_Map
|
|
|
|
else:
|
2021-02-28 12:08:27 -04:00
|
|
|
return [], []
|
2018-01-30 01:24:13 -04:00
|
|
|
except ImportError:
|
|
|
|
print("Unable to find module for MCU %s" % mcu_type)
|
|
|
|
sys.exit(1)
|
|
|
|
|
2019-02-14 06:18:13 -04:00
|
|
|
if dma_map is None:
|
|
|
|
have_DMAMUX = True
|
2020-12-30 08:08:16 -04:00
|
|
|
# ensure we don't assign dma for TIMx_CH as we share that with TIMx_UP
|
|
|
|
timer_ch_periph = [periph for periph in peripheral_list if "_CH" in periph]
|
|
|
|
dma_exclude += timer_ch_periph
|
2021-03-07 23:24:38 -04:00
|
|
|
if mcu_type.startswith("STM32G4"):
|
|
|
|
stream_ofs = 1
|
|
|
|
else:
|
|
|
|
stream_ofs = 0
|
|
|
|
|
|
|
|
dma_map = generate_DMAMUX_map(peripheral_list, noshare_list, dma_exclude, stream_ofs)
|
2019-02-14 06:18:13 -04:00
|
|
|
|
2018-01-30 01:24:13 -04:00
|
|
|
print("Writing DMA map")
|
|
|
|
unassigned = []
|
|
|
|
curr_dict = {}
|
|
|
|
|
2021-03-01 17:52:11 -04:00
|
|
|
# build a map from peripheral name to a list of peripherals that it cannot share with
|
|
|
|
forbidden_map = {}
|
|
|
|
for p in peripheral_list:
|
|
|
|
forbidden_map[p] = forbidden_list(p, peripheral_list)
|
|
|
|
|
2018-01-30 01:24:13 -04:00
|
|
|
for periph in peripheral_list:
|
2020-12-30 08:08:16 -04:00
|
|
|
if "_CH" in periph:
|
|
|
|
has_bdshot = True # the list contains a CH port
|
2018-02-06 03:20:09 -04:00
|
|
|
if periph in dma_exclude:
|
|
|
|
continue
|
2018-01-30 01:24:13 -04:00
|
|
|
assigned = False
|
|
|
|
check_list = []
|
|
|
|
if not periph in dma_map:
|
|
|
|
print("Unknown peripheral function %s in DMA map for %s" %
|
|
|
|
(periph, mcu_type))
|
|
|
|
sys.exit(1)
|
2021-01-17 12:10:59 -04:00
|
|
|
|
|
|
|
if debug:
|
|
|
|
print('\n\n.....Starting lookup for', periph)
|
2018-03-13 21:28:14 -03:00
|
|
|
for streamchan in dma_map[periph]:
|
2021-01-17 12:10:59 -04:00
|
|
|
if debug:
|
|
|
|
print('........Possibility for', periph, streamchan)
|
2018-03-13 21:28:14 -03:00
|
|
|
stream = (streamchan[0], streamchan[1])
|
2018-01-30 01:24:13 -04:00
|
|
|
if check_possibility(periph, stream, curr_dict, dma_map,
|
2021-03-01 17:52:11 -04:00
|
|
|
check_list, [], forbidden_map):
|
2018-01-30 01:24:13 -04:00
|
|
|
curr_dict[periph] = stream
|
2021-01-17 12:10:59 -04:00
|
|
|
if debug:
|
|
|
|
print ('....................... Setting', periph, stream)
|
2018-01-30 01:24:13 -04:00
|
|
|
assigned = True
|
|
|
|
break
|
|
|
|
if assigned == False:
|
|
|
|
unassigned.append(periph)
|
|
|
|
|
2019-02-14 06:18:13 -04:00
|
|
|
if debug:
|
|
|
|
print('curr_dict: ', curr_dict)
|
|
|
|
print('unassigned: ', unassigned)
|
|
|
|
|
2018-02-08 07:13:00 -04:00
|
|
|
# now look for shared DMA possibilities
|
2018-01-30 01:24:13 -04:00
|
|
|
stream_assign = {}
|
2020-10-07 18:46:48 -03:00
|
|
|
for k in sorted(curr_dict.keys()):
|
2019-02-14 06:18:13 -04:00
|
|
|
p = curr_dict[k]
|
|
|
|
if not p in stream_assign:
|
|
|
|
stream_assign[p] = [k]
|
|
|
|
else:
|
|
|
|
stream_assign[p].append(k)
|
2018-01-30 01:24:13 -04:00
|
|
|
|
|
|
|
unassigned_new = unassigned[:]
|
|
|
|
for periph in unassigned:
|
2018-02-08 07:13:00 -04:00
|
|
|
share_possibility = []
|
2018-03-13 21:28:14 -03:00
|
|
|
for streamchan in dma_map[periph]:
|
|
|
|
stream = (streamchan[0], streamchan[1])
|
2018-01-30 01:24:13 -04:00
|
|
|
share_ok = True
|
|
|
|
for periph2 in stream_assign[stream]:
|
2021-03-01 17:52:11 -04:00
|
|
|
if not can_share(periph, noshare_list) or not can_share(periph2, noshare_list) or periph2 in forbidden_map[periph]:
|
2018-01-30 01:24:13 -04:00
|
|
|
share_ok = False
|
|
|
|
if share_ok:
|
2018-02-08 07:13:00 -04:00
|
|
|
share_possibility.append(stream)
|
|
|
|
if share_possibility:
|
|
|
|
# sort the possible sharings so minimise impact on high priority streams
|
|
|
|
share_possibility = sorted(share_possibility, key=lambda x: get_sharing_priority(stream_assign[x], priority_list))
|
|
|
|
# and take the one with the least impact (lowest value for highest priority stream share)
|
|
|
|
stream = share_possibility[-1]
|
|
|
|
if debug:
|
|
|
|
print("Sharing %s on %s with %s" % (periph, stream,
|
|
|
|
stream_assign[stream]))
|
|
|
|
curr_dict[periph] = stream
|
|
|
|
stream_assign[stream].append(periph)
|
|
|
|
unassigned_new.remove(periph)
|
2018-01-30 01:24:13 -04:00
|
|
|
unassigned = unassigned_new
|
|
|
|
|
2021-03-01 17:52:11 -04:00
|
|
|
for key in sorted(curr_dict.keys()):
|
|
|
|
stream = curr_dict[key]
|
|
|
|
if len(stream_assign[stream]) > 1:
|
|
|
|
if not check_sharing(stream_assign[stream]):
|
|
|
|
sys.exit(1)
|
|
|
|
|
2019-02-14 06:18:13 -04:00
|
|
|
if debug:
|
|
|
|
print(stream_assign)
|
|
|
|
|
2018-03-13 21:28:14 -03:00
|
|
|
f.write("\n\n// auto-generated DMA mapping from dma_resolver.py\n")
|
2018-01-30 01:24:13 -04:00
|
|
|
|
|
|
|
if unassigned:
|
|
|
|
f.write(
|
|
|
|
"\n// Note: The following peripherals can't be resolved for DMA: %s\n\n"
|
|
|
|
% unassigned)
|
|
|
|
|
2021-02-28 12:01:01 -04:00
|
|
|
ordered_up_channels = []
|
|
|
|
|
|
|
|
# produce a list of timers ordered by the DMA streamid of the UP channel
|
|
|
|
# this is so that the dshot code can take out the UP DMA locks in the same order as I2C and SPI
|
|
|
|
for key in curr_dict.keys():
|
|
|
|
if "_UP" in key:
|
|
|
|
ordered_up_channels.append(key)
|
|
|
|
|
|
|
|
def order_by_streamid(key):
|
|
|
|
stream = curr_dict[key]
|
|
|
|
return (stream[0] * 8 + stream[1]) * 20 + int(key[3:-3])
|
|
|
|
|
|
|
|
ordered_up_channels = sorted(ordered_up_channels, key=order_by_streamid)
|
|
|
|
ordered_timers = []
|
|
|
|
for key in ordered_up_channels:
|
|
|
|
ordered_timers.append(key[0:-3])
|
|
|
|
|
2021-08-27 21:58:18 -03:00
|
|
|
shared_set = set()
|
|
|
|
|
2018-01-30 01:24:13 -04:00
|
|
|
for key in sorted(curr_dict.keys()):
|
|
|
|
stream = curr_dict[key]
|
|
|
|
shared = ''
|
|
|
|
if len(stream_assign[stream]) > 1:
|
|
|
|
shared = ' // shared %s' % ','.join(stream_assign[stream])
|
2021-08-27 21:58:18 -03:00
|
|
|
if stream[0] in [1,2]:
|
|
|
|
shared_set.add("(1U<<STM32_DMA_STREAM_ID(%u,%u))" % (stream[0],stream[1]))
|
2019-02-06 17:10:40 -04:00
|
|
|
if curr_dict[key] == "STM32_DMA_STREAM_ID_ANY":
|
|
|
|
f.write("#define %-30s STM32_DMA_STREAM_ID_ANY\n" % (chibios_dma_define_name(key)+'STREAM'))
|
2019-02-19 22:55:18 -04:00
|
|
|
f.write("#define %-30s %s\n" % (chibios_dma_define_name(key)+'CHAN', dmamux_channel(key)))
|
2019-02-06 17:10:40 -04:00
|
|
|
continue
|
|
|
|
else:
|
2019-03-02 05:21:36 -04:00
|
|
|
dma_controller = curr_dict[key][0]
|
|
|
|
if dma_controller == 3:
|
2021-08-24 02:18:31 -03:00
|
|
|
# BDMA resources turn out to be very strange on H743. For now
|
|
|
|
# we will skip trying to allocate them automatically and
|
|
|
|
# instead rely on allocation in stm32h7_mcuconf.h.
|
2021-08-20 21:19:16 -03:00
|
|
|
continue
|
|
|
|
else:
|
|
|
|
f.write("#define %-30s STM32_DMA_STREAM_ID(%u, %u)%s\n" %
|
|
|
|
(chibios_dma_define_name(key)+'STREAM', dma_controller,
|
|
|
|
curr_dict[key][1], shared))
|
2020-12-30 08:08:16 -04:00
|
|
|
if have_DMAMUX and "_UP" in key:
|
|
|
|
# share the dma with rest of the _CH ports
|
|
|
|
for ch in range(1,5):
|
|
|
|
chkey = key.replace('_UP', '_CH{}'.format(ch))
|
|
|
|
if chkey not in timer_ch_periph:
|
|
|
|
continue
|
|
|
|
f.write("#define %-30s STM32_DMA_STREAM_ID(%u, %u)%s\n" %
|
|
|
|
(chibios_dma_define_name(chkey)+'STREAM', dma_controller,
|
|
|
|
curr_dict[key][1], shared))
|
2020-10-07 18:46:48 -03:00
|
|
|
for streamchan in sorted(dma_map[key]):
|
2018-03-13 21:28:14 -03:00
|
|
|
if stream == (streamchan[0], streamchan[1]):
|
2019-02-14 06:18:13 -04:00
|
|
|
if have_DMAMUX:
|
2019-02-19 22:55:18 -04:00
|
|
|
chan = dmamux_channel(key)
|
2019-02-14 06:18:13 -04:00
|
|
|
else:
|
|
|
|
chan = streamchan[2]
|
|
|
|
f.write("#define %-30s %s\n" %
|
|
|
|
(chibios_dma_define_name(key)+'CHAN', chan))
|
2020-12-30 08:08:16 -04:00
|
|
|
if have_DMAMUX and "_UP" in key:
|
|
|
|
# share the devid with rest of the _CH ports
|
|
|
|
for ch in range(1,5):
|
|
|
|
chkey = key.replace('_UP', '_CH{}'.format(ch))
|
|
|
|
if chkey not in timer_ch_periph:
|
|
|
|
continue
|
|
|
|
f.write("#define %-30s %s\n" %
|
|
|
|
(chibios_dma_define_name(chkey)+'CHAN',
|
|
|
|
chan.replace('_UP', '_CH{}'.format(ch))))
|
2018-03-13 21:28:14 -03:00
|
|
|
break
|
2018-01-30 01:24:13 -04:00
|
|
|
|
2021-08-27 21:58:18 -03:00
|
|
|
f.write("\n// Mask of DMA streams which are shared\n")
|
|
|
|
if len(shared_set) == 0:
|
|
|
|
f.write("#define SHARED_DMA_MASK 0\n")
|
|
|
|
else:
|
2021-12-12 19:16:34 -04:00
|
|
|
f.write("#define SHARED_DMA_MASK (%s)\n" % '|'.join(sorted(list(shared_set))))
|
2021-08-27 21:58:18 -03:00
|
|
|
|
2019-02-20 02:17:38 -04:00
|
|
|
# now generate UARTDriver.cpp DMA config lines
|
2018-01-30 01:24:13 -04:00
|
|
|
f.write("\n\n// generated UART DMA configuration lines\n")
|
|
|
|
for u in range(1, 9):
|
|
|
|
key = None
|
|
|
|
if 'USART%u_TX' % u in peripheral_list:
|
|
|
|
key = 'USART%u' % u
|
|
|
|
if 'UART%u_TX' % u in peripheral_list:
|
|
|
|
key = 'UART%u' % u
|
|
|
|
if 'USART%u_RX' % u in peripheral_list:
|
|
|
|
key = 'USART%u' % u
|
|
|
|
if 'UART%u_RX' % u in peripheral_list:
|
|
|
|
key = 'UART%u' % u
|
|
|
|
if key is None:
|
|
|
|
continue
|
2019-02-14 06:18:13 -04:00
|
|
|
if have_DMAMUX:
|
2019-02-13 19:13:00 -04:00
|
|
|
# use DMAMUX ID as channel number
|
2019-02-19 22:55:18 -04:00
|
|
|
dma_rx_chn = dmamux_channel(key + "_RX")
|
|
|
|
dma_tx_chn = dmamux_channel(key + "_TX")
|
2019-02-06 17:10:40 -04:00
|
|
|
else:
|
2019-02-19 22:55:18 -04:00
|
|
|
dma_rx_chn = "STM32_UART_%s_RX_%s_CHAN" % (key, dma_name(key))
|
|
|
|
dma_tx_chn = "STM32_UART_%s_TX_%s_CHAN" % (key, dma_name(key))
|
2019-02-06 17:10:40 -04:00
|
|
|
|
2018-01-30 01:24:13 -04:00
|
|
|
f.write("#define STM32_%s_RX_DMA_CONFIG " % key)
|
|
|
|
if key + "_RX" in curr_dict:
|
|
|
|
f.write(
|
2019-02-19 22:55:18 -04:00
|
|
|
"true, STM32_UART_%s_RX_%s_STREAM, %s\n" % (key, dma_name(key), dma_rx_chn))
|
2018-01-30 01:24:13 -04:00
|
|
|
else:
|
|
|
|
f.write("false, 0, 0\n")
|
|
|
|
f.write("#define STM32_%s_TX_DMA_CONFIG " % key)
|
|
|
|
if key + "_TX" in curr_dict:
|
|
|
|
f.write(
|
2019-02-19 22:55:18 -04:00
|
|
|
"true, STM32_UART_%s_TX_%s_STREAM, %s\n" % (key, dma_name(key), dma_tx_chn))
|
2018-01-30 01:24:13 -04:00
|
|
|
else:
|
|
|
|
f.write("false, 0, 0\n")
|
2018-01-05 02:19:51 -04:00
|
|
|
|
2019-02-20 02:17:38 -04:00
|
|
|
# now generate SPI DMA streams lines
|
|
|
|
f.write("\n\n// generated SPI DMA configuration lines\n")
|
|
|
|
for u in range(1, 9):
|
|
|
|
if 'SPI%u_TX' % u in peripheral_list and 'SPI%u_RX' % u in peripheral_list:
|
|
|
|
key = 'SPI%u' % u
|
|
|
|
else:
|
|
|
|
continue
|
2021-08-24 02:18:31 -03:00
|
|
|
if dma_name(key) == 'BDMA':
|
|
|
|
# we use SHARED_DMA_NONE for SPI6 on H7 as we don't need to lock the stream
|
|
|
|
# as it is never shared
|
|
|
|
f.write('#define STM32_SPI_%s_DMA_STREAMS SHARED_DMA_NONE, SHARED_DMA_NONE\n' % key)
|
|
|
|
else:
|
|
|
|
f.write('#define STM32_SPI_%s_DMA_STREAMS STM32_SPI_%s_TX_%s_STREAM, STM32_SPI_%s_RX_%s_STREAM\n' % (
|
|
|
|
key, key, dma_name(key), key, dma_name(key)))
|
2021-02-28 12:01:01 -04:00
|
|
|
return unassigned, ordered_timers
|
2019-02-20 02:17:38 -04:00
|
|
|
|
|
|
|
|
2018-01-05 02:19:51 -04:00
|
|
|
if __name__ == '__main__':
|
2018-01-30 01:24:13 -04:00
|
|
|
import optparse
|
2018-01-05 02:19:51 -04:00
|
|
|
|
2018-01-30 01:24:13 -04:00
|
|
|
parser = optparse.OptionParser("dma_resolver.py")
|
|
|
|
parser.add_option("-M", "--mcu", default=None, help='MCU type')
|
|
|
|
parser.add_option(
|
|
|
|
"-D", "--debug", action='store_true', help='enable debug')
|
|
|
|
parser.add_option(
|
|
|
|
"-P",
|
|
|
|
"--peripherals",
|
|
|
|
default=None,
|
|
|
|
help='peripheral list (comma separated)')
|
2018-01-05 02:19:51 -04:00
|
|
|
|
2018-01-30 01:24:13 -04:00
|
|
|
opts, args = parser.parse_args()
|
2018-01-05 02:19:51 -04:00
|
|
|
|
2018-01-30 01:24:13 -04:00
|
|
|
if opts.peripherals is None:
|
|
|
|
print("Please provide a peripheral list with -P")
|
|
|
|
sys.exit(1)
|
2018-01-05 02:19:51 -04:00
|
|
|
|
2018-01-30 01:24:13 -04:00
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if opts.mcu is None:
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print("Please provide a MCU type with -<")
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sys.exit(1)
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2018-01-05 02:19:51 -04:00
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2018-01-30 01:24:13 -04:00
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debug = opts.debug
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2018-01-05 02:19:51 -04:00
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2018-01-30 01:24:13 -04:00
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plist = opts.peripherals.split(',')
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|
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mcu_type = opts.mcu
|
2018-01-05 02:19:51 -04:00
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2018-01-30 01:24:13 -04:00
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f = open("dma.h", "w")
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|
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write_dma_header(f, plist, mcu_type)
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2018-02-06 03:20:09 -04:00
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