2024-05-27 16:54:26 -03:00
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# hw definition file for processing by chibios_pins.py
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include ../iomcu-dshot/hwdef.inc
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undef STM32_ST_USE_TIMER
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# directly define DMA channels
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DMA_NOMAP 1
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# only four timers on F103xB so use TIM1 for system timer
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STM32_ST_USE_TIMER 1
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define HAL_WITH_ESC_TELEM 1
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undef PA0 PA1 PB8 PB9
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# the order is important here as it determines the order that timers are used to sending dshot
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# TIM4 needs to go first so that TIM4_UP can be freed up to be used by input capture for TIM2
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PB8 TIM4_CH3 TIM4 PWM(3) GPIO(103) BIDIR UP_SHARED
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PB9 TIM4_CH4 TIM4 PWM(4) GPIO(104)
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PA0 TIM2_CH1 TIM2 PWM(1) GPIO(101)
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PA1 TIM2_CH2 TIM2 PWM(2) GPIO(102) BIDIR # DMA channel 7, shared with TIM4_UP and USART2_TX
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# currently no support for having mixed outputs on the same timer
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# PB1 TIM3_CH4 TIM3 PWM(8) GPIO(108) BIDIR # DMA channel 3, shared with TIM3_UP
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# TIM2_UP - (1,2)
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# TIM4_UP - (1,7)
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# TIM3_UP - (1,3)
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# TIM2_CH2 (PWM 1/2)
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define STM32_TIM_TIM2_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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define STM32_TIM_TIM2_CH2_DMA_CHAN 1
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# TIM4_CH3 (PWM 3/4)
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define STM32_TIM_TIM4_CH3_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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define STM32_TIM_TIM4_CH3_DMA_CHAN 1
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# TIM3_CH4 (PWM 7-8)
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define STM32_TIM_TIM3_CH4_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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define STM32_TIM_TIM3_CH4_DMA_CHAN 1
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2024-05-30 12:30:59 -03:00
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# STM32_UART_USART2_TX_DMA_STREAM defined as (1, 7) by ChibiOS
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2024-05-27 16:54:26 -03:00
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undef SHARED_DMA_MASK
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define SHARED_DMA_MASK (1U<<STM32_TIM_TIM4_UP_DMA_STREAM | 1U<<STM32_TIM_TIM2_CH2_DMA_STREAM | 1U<<STM32_UART_USART2_TX_DMA_STREAM)
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undef MAIN_STACK
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MAIN_STACK 0x400
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