2012-08-27 15:44:50 -03:00
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#ifndef __AP_HAL_RC_OUTPUT_H__
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#define __AP_HAL_RC_OUTPUT_H__
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#include "AP_HAL_Namespace.h"
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2012-08-28 01:05:19 -03:00
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/* Define the CH_n names, indexed from 1, if we don't have them already */
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#ifndef CH_1
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#define CH_1 0
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#define CH_2 1
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#define CH_3 2
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#define CH_4 3
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#define CH_5 4
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#define CH_6 5
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#define CH_7 6
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#define CH_8 7
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#define CH_9 8
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#define CH_10 9
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#define CH_11 10
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2013-04-25 06:58:49 -03:00
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#define CH_12 11
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2014-03-25 00:39:41 -03:00
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#define CH_13 12
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#define CH_14 13
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#define CH_15 14
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#define CH_16 15
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#define CH_17 16
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#define CH_18 17
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2012-08-28 01:05:19 -03:00
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#endif
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2012-08-27 15:44:50 -03:00
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class AP_HAL::RCOutput {
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public:
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2012-08-27 20:45:46 -03:00
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virtual void init(void* implspecific) = 0;
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/* Output freq (1/period) control */
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virtual void set_freq(uint32_t chmask, uint16_t freq_hz) = 0;
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virtual uint16_t get_freq(uint8_t ch) = 0;
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/* Output active/highZ control, either by single channel at a time
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* or a mask of channels */
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virtual void enable_ch(uint8_t ch) = 0;
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virtual void disable_ch(uint8_t ch) = 0;
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/* Output, either single channel or bulk array of channels */
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2012-08-28 01:05:19 -03:00
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virtual void write(uint8_t ch, uint16_t period_us) = 0;
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virtual void write(uint8_t ch, uint16_t* period_us, uint8_t len) = 0;
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2012-08-27 20:45:46 -03:00
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/* Read back current output state, as either single channel or
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* array of channels. */
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virtual uint16_t read(uint8_t ch) = 0;
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2012-08-28 01:05:19 -03:00
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virtual void read(uint16_t* period_us, uint8_t len) = 0;
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2014-01-15 07:25:22 -04:00
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/*
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set PWM to send to a set of channels when the safety switch is
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in the safe state
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*/
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virtual void set_safety_pwm(uint32_t chmask, uint16_t period_us) {}
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2014-02-11 00:56:44 -04:00
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2014-04-20 19:36:52 -03:00
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/*
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set PWM to send to a set of channels if the FMU firmware dies
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*/
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virtual void set_failsafe_pwm(uint32_t chmask, uint16_t period_us) {}
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2014-02-11 00:56:44 -04:00
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/*
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force the safety switch off, enabling PWM output from the IO board
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*/
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virtual void force_safety_off(void) {}
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2012-08-27 15:44:50 -03:00
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};
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#endif // __AP_HAL_RC_OUTPUT_H__
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