2018-06-21 19:06:29 -03:00
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/*
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support tables for STM32F4
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*/
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#if defined(STM32F4)
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/* magic numbers from reference manual */
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enum {
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MCU_REV_STM32F4_REV_A = 0x1000,
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MCU_REV_STM32F4_REV_Z = 0x1001,
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MCU_REV_STM32F4_REV_Y = 0x1003,
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MCU_REV_STM32F4_REV_1 = 0x1007,
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MCU_REV_STM32F4_REV_3 = 0x2001
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};
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#define STM32_UNKNOWN 0
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#define STM32F40x_41x 0x413
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#define STM32F42x_43x 0x419
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#define STM32F42x_446xx 0x421
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// The default CPU ID of STM32_UNKNOWN is 0 and is in offset 0
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// There for new silicon will result in STM32F4..,?
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const mcu_des_t mcu_descriptions[] = {
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2023-04-14 07:54:34 -03:00
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{ STM32_UNKNOWN, "STM32F???" },
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{ STM32F40x_41x, "STM32F40x" },
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{ STM32F42x_43x, "STM32F42x" },
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{ STM32F42x_446xx, "STM32F446XX" },
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2018-06-21 19:06:29 -03:00
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};
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const mcu_rev_t silicon_revs[] = {
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2022-10-04 03:43:46 -03:00
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{MCU_REV_STM32F4_REV_3, '3'}, /* Revision 3 */
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2018-06-21 19:06:29 -03:00
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2022-10-04 03:43:46 -03:00
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{MCU_REV_STM32F4_REV_A, 'A'}, /* Revision A */
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{MCU_REV_STM32F4_REV_Z, 'Z'}, /* Revision Z */
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{MCU_REV_STM32F4_REV_Y, 'Y'}, /* Revision Y */
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{MCU_REV_STM32F4_REV_1, '1'}, /* Revision 1 */
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2018-06-21 19:06:29 -03:00
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};
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#endif // STM32F4
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