2011-11-12 07:13:17 -04:00
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LOG_BITMASK 4095
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SWITCH_ENABLE 0
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2011-12-02 00:21:15 -04:00
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MAG_ENABLE 0
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TRIM_ARSPD_CM 2200
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ARSPD_ENABLE 1
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ARSP2PTCH_I 0.1
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ARSPD_FBW_MAX 30
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ARSPD_FBW_MIN 10
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KFF_RDDRMIX 0
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KFF_PTCHCOMP 0.2
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THR_MAX 100
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2011-11-12 07:13:17 -04:00
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RC2_REV -1
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2011-12-06 07:54:12 -04:00
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RC4_REV -1
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2011-11-12 07:13:17 -04:00
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RC1_MAX 2000
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RC1_MIN 1000
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RC1_TRIM 1500
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RC2_MAX 2000
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RC2_MIN 1000
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RC2_TRIM 1500
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RC3_MAX 2000
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RC3_MIN 1000
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2011-12-06 07:54:12 -04:00
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RC3_TRIM 1000
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2011-11-12 07:13:17 -04:00
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RC4_MAX 2000
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RC4_MIN 1000
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RC4_TRIM 1500
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RC5_MAX 2000
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RC5_MIN 1000
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RC5_TRIM 1500
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RC6_MAX 2000
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RC6_MIN 1000
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RC6_TRIM 1500
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RC7_MAX 2000
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RC7_MIN 1000
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RC7_TRIM 1500
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RC8_MAX 2000
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RC8_MIN 1000
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RC8_TRIM 1500
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FLTMODE1 10
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FLTMODE2 11
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FLTMODE3 12
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FLTMODE4 5
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FLTMODE5 2
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FLTMODE6 0
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FLTMODE_CH 8
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PTCH2SRV_P 2
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2011-12-02 00:21:15 -04:00
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RLL2SRV_I 0
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2011-11-12 07:13:17 -04:00
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RLL2SRV_P 1.2
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