2018-01-05 02:19:51 -04:00
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/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Code by Andrew Tridgell and Siddharth Bharat Purohit
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*/
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#include "shared_dma.h"
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/*
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code to handle sharing of DMA channels between peripherals
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*/
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2018-08-29 10:14:12 -03:00
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#if CH_CFG_USE_SEMAPHORES == TRUE && STM32_DMA_ADVANCED
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2018-03-28 23:07:50 -03:00
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2018-01-13 00:02:05 -04:00
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using namespace ChibiOS;
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2019-02-09 17:51:13 -04:00
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Shared_DMA::dma_lock Shared_DMA::locks[SHARED_DMA_MAX_STREAM_ID+1];
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2018-01-05 02:19:51 -04:00
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void Shared_DMA::init(void)
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{
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for (uint8_t i=0; i<SHARED_DMA_MAX_STREAM_ID; i++) {
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chBSemObjectInit(&locks[i].semaphore, false);
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}
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}
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// constructor
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Shared_DMA::Shared_DMA(uint8_t _stream_id1,
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uint8_t _stream_id2,
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dma_allocate_fn_t _allocate,
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dma_deallocate_fn_t _deallocate)
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{
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stream_id1 = _stream_id1;
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stream_id2 = _stream_id2;
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allocate = _allocate;
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deallocate = _deallocate;
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}
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//remove any assigned deallocator or allocator
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void Shared_DMA::unregister()
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{
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2019-02-10 03:04:57 -04:00
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if (stream_id1 < SHARED_DMA_MAX_STREAM_ID &&
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locks[stream_id1].obj == this) {
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2018-03-14 03:06:30 -03:00
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locks[stream_id1].deallocate(this);
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2018-01-05 02:19:51 -04:00
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locks[stream_id1].obj = nullptr;
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}
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2019-02-10 03:04:57 -04:00
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if (stream_id2 < SHARED_DMA_MAX_STREAM_ID &&
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locks[stream_id2].obj == this) {
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2018-03-14 03:06:30 -03:00
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locks[stream_id2].deallocate(this);
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2018-01-05 02:19:51 -04:00
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locks[stream_id2].obj = nullptr;
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}
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}
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2019-02-09 17:51:13 -04:00
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// lock one stream
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void Shared_DMA::lock_stream(uint8_t stream_id)
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{
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2019-02-10 03:04:57 -04:00
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if (stream_id < SHARED_DMA_MAX_STREAM_ID) {
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2019-02-09 17:51:13 -04:00
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chBSemWait(&locks[stream_id].semaphore);
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}
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}
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// unlock one stream
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void Shared_DMA::unlock_stream(uint8_t stream_id)
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{
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2019-02-10 03:04:57 -04:00
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if (stream_id < SHARED_DMA_MAX_STREAM_ID) {
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2019-02-09 17:51:13 -04:00
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chBSemSignal(&locks[stream_id].semaphore);
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}
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}
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// unlock one stream from an IRQ handler
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void Shared_DMA::unlock_stream_from_IRQ(uint8_t stream_id)
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{
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2019-02-10 03:04:57 -04:00
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if (stream_id < SHARED_DMA_MAX_STREAM_ID) {
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2019-02-09 17:51:13 -04:00
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chBSemSignalI(&locks[stream_id].semaphore);
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}
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}
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// lock one stream, non-blocking
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bool Shared_DMA::lock_stream_nonblocking(uint8_t stream_id)
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{
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2019-02-10 03:04:57 -04:00
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if (stream_id < SHARED_DMA_MAX_STREAM_ID) {
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2019-02-09 17:51:13 -04:00
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return chBSemWaitTimeout(&locks[stream_id].semaphore, 1) == MSG_OK;
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}
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return true;
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}
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2018-01-05 02:19:51 -04:00
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// lock the DMA channels
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2018-03-02 06:34:57 -04:00
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void Shared_DMA::lock_core(void)
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2018-01-05 02:19:51 -04:00
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{
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// see if another driver has DMA allocated. If so, call their
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// deallocation function
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2019-02-10 03:04:57 -04:00
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if (stream_id1 < SHARED_DMA_MAX_STREAM_ID &&
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2018-01-05 02:19:51 -04:00
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locks[stream_id1].obj && locks[stream_id1].obj != this) {
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2018-03-14 03:06:30 -03:00
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locks[stream_id1].deallocate(locks[stream_id1].obj);
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2018-01-05 02:19:51 -04:00
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locks[stream_id1].obj = nullptr;
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}
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2019-02-10 03:04:57 -04:00
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if (stream_id2 < SHARED_DMA_MAX_STREAM_ID &&
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2018-01-05 02:19:51 -04:00
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locks[stream_id2].obj && locks[stream_id2].obj != this) {
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2018-03-14 03:06:30 -03:00
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locks[stream_id2].deallocate(locks[stream_id2].obj);
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2018-01-05 02:19:51 -04:00
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locks[stream_id2].obj = nullptr;
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}
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2019-02-10 03:04:57 -04:00
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if ((stream_id1 < SHARED_DMA_MAX_STREAM_ID && locks[stream_id1].obj == nullptr) ||
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(stream_id2 < SHARED_DMA_MAX_STREAM_ID && locks[stream_id2].obj == nullptr)) {
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2018-01-05 02:19:51 -04:00
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// allocate the DMA channels and put our deallocation function in place
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2018-03-14 03:06:30 -03:00
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allocate(this);
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2019-02-10 17:01:12 -04:00
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if (stream_id1 < SHARED_DMA_MAX_STREAM_ID) {
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2018-01-05 02:19:51 -04:00
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locks[stream_id1].deallocate = deallocate;
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locks[stream_id1].obj = this;
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}
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2019-02-10 17:01:12 -04:00
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if (stream_id2 < SHARED_DMA_MAX_STREAM_ID) {
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2018-01-05 02:19:51 -04:00
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locks[stream_id2].deallocate = deallocate;
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locks[stream_id2].obj = this;
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}
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2019-02-13 03:44:45 -04:00
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}
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#ifdef STM32_DMA_STREAM_ID_ANY
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else if (stream_id1 == STM32_DMA_STREAM_ID_ANY ||
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stream_id2 == STM32_DMA_STREAM_ID_ANY) {
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2019-02-10 03:04:57 -04:00
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// call allocator without needing locking
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allocate(this);
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2018-01-05 02:19:51 -04:00
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}
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2019-02-13 03:44:45 -04:00
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#endif
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2018-02-05 23:59:10 -04:00
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have_lock = true;
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2018-01-05 02:19:51 -04:00
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}
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2018-03-02 06:34:57 -04:00
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// lock the DMA channels, blocking method
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void Shared_DMA::lock(void)
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{
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2019-02-10 17:01:12 -04:00
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lock_stream(stream_id1);
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lock_stream(stream_id2);
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2018-03-02 06:34:57 -04:00
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lock_core();
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}
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// lock the DMA channels, non-blocking
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bool Shared_DMA::lock_nonblock(void)
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{
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2019-02-10 17:01:12 -04:00
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if (!lock_stream_nonblocking(stream_id1)) {
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chSysDisable();
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if (locks[stream_id1].obj != nullptr && locks[stream_id1].obj != this) {
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locks[stream_id1].obj->contention = true;
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2018-03-02 06:34:57 -04:00
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}
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2019-02-10 17:01:12 -04:00
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chSysEnable();
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contention = true;
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return false;
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2018-03-02 06:34:57 -04:00
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}
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2019-02-10 17:01:12 -04:00
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if (!lock_stream_nonblocking(stream_id2)) {
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unlock_stream(stream_id1);
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chSysDisable();
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if (locks[stream_id2].obj != nullptr && locks[stream_id2].obj != this) {
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locks[stream_id2].obj->contention = true;
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2018-03-02 06:34:57 -04:00
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}
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2019-02-10 17:01:12 -04:00
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chSysEnable();
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contention = true;
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return false;
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2018-03-02 06:34:57 -04:00
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}
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lock_core();
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return true;
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}
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2018-01-05 02:19:51 -04:00
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// unlock the DMA channels
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void Shared_DMA::unlock(void)
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{
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2018-02-05 23:59:10 -04:00
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osalDbgAssert(have_lock, "must have lock");
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2019-02-10 17:01:12 -04:00
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unlock_stream(stream_id2);
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unlock_stream(stream_id1);
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2018-02-05 23:59:10 -04:00
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have_lock = false;
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}
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// unlock the DMA channels from a lock zone
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void Shared_DMA::unlock_from_lockzone(void)
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{
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osalDbgAssert(have_lock, "must have lock");
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2019-02-10 17:01:12 -04:00
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if (stream_id2 < SHARED_DMA_MAX_STREAM_ID) {
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2019-02-09 17:51:13 -04:00
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unlock_stream_from_IRQ(stream_id2);
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2018-02-05 23:59:10 -04:00
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chSchRescheduleS();
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}
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2019-02-10 17:01:12 -04:00
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if (stream_id1 < SHARED_DMA_MAX_STREAM_ID) {
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2019-02-09 17:51:13 -04:00
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unlock_stream_from_IRQ(stream_id1);
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2018-02-05 23:59:10 -04:00
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chSchRescheduleS();
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}
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have_lock = false;
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2018-01-05 02:19:51 -04:00
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}
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// unlock the DMA channels from an IRQ
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void Shared_DMA::unlock_from_IRQ(void)
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{
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2018-02-05 23:59:10 -04:00
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osalDbgAssert(have_lock, "must have lock");
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2019-02-10 17:01:12 -04:00
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unlock_stream_from_IRQ(stream_id2);
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unlock_stream_from_IRQ(stream_id1);
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2018-02-05 23:59:10 -04:00
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have_lock = false;
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2018-01-05 02:19:51 -04:00
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}
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2018-01-28 21:43:55 -04:00
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/*
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lock all channels - used on reboot to ensure no sensor DMA is in
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progress
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*/
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void Shared_DMA::lock_all(void)
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{
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for (uint8_t i=0; i<SHARED_DMA_MAX_STREAM_ID; i++) {
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2019-02-09 17:51:13 -04:00
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lock_stream(i);
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2018-01-28 21:43:55 -04:00
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}
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}
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2018-03-28 23:07:50 -03:00
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2018-08-29 10:14:12 -03:00
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#endif // CH_CFG_USE_SEMAPHORES && STM32_DMA_ADVANCED
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