2015-08-18 00:29:58 -03:00
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#include <AP_HAL/AP_HAL.h>
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#if CONFIG_HAL_BOARD == HAL_BOARD_LINUX
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2015-10-20 14:04:59 -03:00
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#include "RPIOUARTDriver.h"
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2015-08-18 00:29:58 -03:00
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#include <stdlib.h>
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#include <cstdio>
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2015-10-20 14:04:59 -03:00
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#include <AP_HAL/utility/RingBuffer.h>
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2015-08-18 00:29:58 -03:00
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#include "px4io_protocol.h"
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#define RPIOUART_POLL_TIME_INTERVAL 10000
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extern const AP_HAL::HAL& hal;
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#define RPIOUART_DEBUG 0
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#include <cassert>
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#if RPIOUART_DEBUG
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#define debug(fmt, args ...) do {hal.console->printf("[RPIOUARTDriver]: %s:%d: " fmt "\n", __FUNCTION__, __LINE__, ## args); } while(0)
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#define error(fmt, args ...) do {fprintf(stderr,"%s:%d: " fmt "\n", __FUNCTION__, __LINE__, ## args); } while(0)
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#else
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#define debug(fmt, args ...)
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#define error(fmt, args ...)
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#endif
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using namespace Linux;
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2015-10-20 18:13:25 -03:00
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RPIOUARTDriver::RPIOUARTDriver() :
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UARTDriver(false),
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2015-08-18 00:29:58 -03:00
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_spi(NULL),
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_spi_sem(NULL),
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_last_update_timestamp(0),
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_external(false),
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_need_set_baud(false),
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_baudrate(0)
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{
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_readbuf = NULL;
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_writebuf = NULL;
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}
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bool RPIOUARTDriver::sem_take_nonblocking()
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{
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return _spi_sem->take_nonblocking();
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}
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2015-10-20 18:13:25 -03:00
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void RPIOUARTDriver::sem_give()
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{
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_spi_sem->give();
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}
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2015-10-20 18:13:25 -03:00
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bool RPIOUARTDriver::isExternal()
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{
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return _external;
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}
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2015-10-20 18:13:25 -03:00
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void RPIOUARTDriver::begin(uint32_t b, uint16_t rxS, uint16_t txS)
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{
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//hal.console->printf("[RPIOUARTDriver]: begin \n");
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if (device_path != NULL) {
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UARTDriver::begin(b,rxS,txS);
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if ( is_initialized()) {
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_external = true;
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return;
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}
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}
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if (rxS < 1024) {
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rxS = 2048;
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}
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if (txS < 1024) {
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txS = 2048;
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}
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_initialised = false;
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while (_in_timer) hal.scheduler->delay(1);
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/*
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allocate the read buffer
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*/
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if (rxS != 0 && rxS != _readbuf_size) {
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_readbuf_size = rxS;
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if (_readbuf != NULL) {
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free(_readbuf);
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}
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_readbuf = (uint8_t *)malloc(_readbuf_size);
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_readbuf_head = 0;
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_readbuf_tail = 0;
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}
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/*
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allocate the write buffer
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*/
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if (txS != 0 && txS != _writebuf_size) {
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_writebuf_size = txS;
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if (_writebuf != NULL) {
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free(_writebuf);
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}
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_writebuf = (uint8_t *)malloc(_writebuf_size);
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_writebuf_head = 0;
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_writebuf_tail = 0;
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}
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_spi = hal.spi->device(AP_HAL::SPIDevice_RASPIO);
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if (_spi == NULL) {
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AP_HAL::panic("Cannot get SPIDevice_RASPIO");
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}
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_spi_sem = _spi->get_semaphore();
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if (_spi_sem == NULL) {
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AP_HAL::panic("PANIC: RASPIOUARTDriver did not get "
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"valid SPI semaphore!");
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return; // never reached
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}
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/* set baudrate */
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_baudrate = b;
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_need_set_baud = true;
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while (_need_set_baud) {
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hal.scheduler->delay(1);
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}
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if (_writebuf_size != 0 && _readbuf_size != 0) {
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_initialised = true;
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}
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}
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2015-10-20 18:13:25 -03:00
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int RPIOUARTDriver::_write_fd(const uint8_t *buf, uint16_t n)
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{
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if (_external) {
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return UARTDriver::_write_fd(buf, n);
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}
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return -1;
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}
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int RPIOUARTDriver::_read_fd(uint8_t *buf, uint16_t n)
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{
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if (_external) {
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return UARTDriver::_read_fd(buf, n);
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}
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return -1;
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}
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2015-10-20 18:13:25 -03:00
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void RPIOUARTDriver::_timer_tick(void)
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{
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if (_external) {
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UARTDriver::_timer_tick();
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return;
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}
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/* set the baudrate of raspilotio */
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if (_need_set_baud) {
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if (_baudrate != 0) {
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if (!_spi_sem->take_nonblocking()) {
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return;
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}
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struct IOPacket _dma_packet_tx, _dma_packet_rx;
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_dma_packet_tx.count_code = 2 | PKT_CODE_WRITE;
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_dma_packet_tx.page = PX4IO_PAGE_UART_BUFFER;
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_dma_packet_tx.offset = 0;
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_dma_packet_tx.regs[0] = _baudrate & 0xffff;
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_dma_packet_tx.regs[1] = _baudrate >> 16;
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_dma_packet_tx.crc = 0;
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_dma_packet_tx.crc = crc_packet(&_dma_packet_tx);
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_spi->transaction((uint8_t *)&_dma_packet_tx, (uint8_t *)&_dma_packet_rx, sizeof(_dma_packet_tx));
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hal.scheduler->delay(1);
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_spi_sem->give();
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}
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_need_set_baud = false;
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}
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/* finish set */
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if (!_initialised) return;
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/* lower the update rate */
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if (AP_HAL::micros() - _last_update_timestamp < RPIOUART_POLL_TIME_INTERVAL) {
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return;
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}
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_in_timer = true;
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if (!_spi_sem->take_nonblocking()) {
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return;
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}
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struct IOPacket _dma_packet_tx, _dma_packet_rx;
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/* get write_buf bytes */
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uint16_t _tail;
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uint16_t n = BUF_AVAILABLE(_writebuf);
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if (n > PKT_MAX_REGS * 2) {
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n = PKT_MAX_REGS * 2;
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}
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uint16_t _max_size = _baudrate / 10 / (1000000 / RPIOUART_POLL_TIME_INTERVAL);
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if (n > _max_size) {
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n = _max_size;
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}
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if (n > 0) {
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uint16_t n1 = _writebuf_size - _writebuf_head;
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if (n1 >= n) {
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// do as a single write
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memcpy( &((uint8_t *)_dma_packet_tx.regs)[0], &_writebuf[_writebuf_head], n );
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} else {
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// split into two writes
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memcpy( &((uint8_t *)_dma_packet_tx.regs)[0], &_writebuf[_writebuf_head], n1 );
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memcpy( &((uint8_t *)_dma_packet_tx.regs)[n1], &_writebuf[0], n-n1 );
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}
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BUF_ADVANCEHEAD(_writebuf, n);
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}
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_dma_packet_tx.count_code = PKT_MAX_REGS | PKT_CODE_SPIUART;
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_dma_packet_tx.page = PX4IO_PAGE_UART_BUFFER;
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_dma_packet_tx.offset = n;
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/* end get write_buf bytes */
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_dma_packet_tx.crc = 0;
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_dma_packet_tx.crc = crc_packet(&_dma_packet_tx);
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/* set raspilotio to read uart data */
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_spi->transaction((uint8_t *)&_dma_packet_tx, (uint8_t *)&_dma_packet_rx, sizeof(_dma_packet_tx));
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hal.scheduler->delay_microseconds(100);
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/* get uart data from raspilotio */
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_dma_packet_tx.count_code = 0 | PKT_CODE_READ;
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_dma_packet_tx.page = 0;
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_dma_packet_tx.offset = 0;
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memset( &_dma_packet_tx.regs[0], 0, PKT_MAX_REGS*sizeof(uint16_t) );
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_dma_packet_tx.crc = 0;
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_dma_packet_tx.crc = crc_packet(&_dma_packet_tx);
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_spi->transaction((uint8_t *)&_dma_packet_tx, (uint8_t *)&_dma_packet_rx, sizeof(_dma_packet_tx));
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hal.scheduler->delay_microseconds(100);
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/* release sem */
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_spi_sem->give();
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/* add bytes to read buf */
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uint16_t _head;
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n = BUF_SPACE(_readbuf);
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if (_dma_packet_rx.page == PX4IO_PAGE_UART_BUFFER) {
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if (n > _dma_packet_rx.offset) {
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n = _dma_packet_rx.offset;
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}
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if (n > PKT_MAX_REGS * 2) {
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n = PKT_MAX_REGS * 2;
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}
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if (n > 0) {
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uint16_t n1 = _readbuf_size - _readbuf_tail;
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if (n1 >= n) {
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// one read will do
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memcpy( &_readbuf[_readbuf_tail], &((uint8_t *)_dma_packet_rx.regs)[0], n );
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} else {
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memcpy( &_readbuf[_readbuf_tail], &((uint8_t *)_dma_packet_rx.regs)[0], n1 );
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memcpy( &_readbuf[0], &((uint8_t *)_dma_packet_rx.regs)[n1], n-n1 );
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}
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BUF_ADVANCETAIL(_readbuf, n);
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}
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}
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_in_timer = false;
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2015-11-19 23:10:58 -04:00
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_last_update_timestamp = AP_HAL::micros();
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2015-08-18 00:29:58 -03:00
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}
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#endif
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