2013-01-21 19:50:26 -04:00
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/// -*- tab-width: 4; Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil -*-
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2013-01-02 20:03:05 -04:00
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#include <AP_HAL.h>
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#if CONFIG_HAL_BOARD == HAL_BOARD_PX4
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#include "UARTDriver.h"
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2013-01-03 02:27:53 -04:00
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2013-01-02 20:03:05 -04:00
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#include <stdio.h>
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#include <unistd.h>
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2013-01-03 02:27:53 -04:00
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#include <stdlib.h>
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2013-01-03 06:12:10 -04:00
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#include <errno.h>
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#include <sys/ioctl.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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2013-01-04 04:42:30 -04:00
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#include <termios.h>
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2013-02-18 21:02:46 -04:00
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#include <drivers/drv_hrt.h>
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2013-02-20 03:15:56 -04:00
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#include <assert.h>
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2013-01-02 20:03:05 -04:00
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using namespace PX4;
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2013-01-03 06:12:10 -04:00
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extern const AP_HAL::HAL& hal;
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2013-01-24 00:01:48 -04:00
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PX4UARTDriver::PX4UARTDriver(const char *devpath, const char *perf_name) :
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_devpath(devpath),
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2013-10-05 02:47:28 -03:00
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_fd(-1),
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_baudrate(57600),
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_perf_uart(perf_alloc(PC_ELAPSED, perf_name)),
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_initialised(false),
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2014-02-10 20:22:08 -04:00
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_in_timer(false),
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_flow_control(FLOW_CONTROL_DISABLE)
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2013-10-05 02:47:28 -03:00
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{
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}
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2013-01-24 00:01:48 -04:00
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2013-01-02 20:03:05 -04:00
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2013-01-03 02:27:53 -04:00
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extern const AP_HAL::HAL& hal;
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2013-01-02 20:03:05 -04:00
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/*
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2013-01-04 04:42:30 -04:00
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this UART driver maps to a serial device in /dev
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2013-01-02 20:03:05 -04:00
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*/
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2013-01-04 04:42:30 -04:00
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void PX4UARTDriver::begin(uint32_t b, uint16_t rxS, uint16_t txS)
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{
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2013-11-22 04:16:51 -04:00
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if (strcmp(_devpath, "/dev/null") == 0) {
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// leave uninitialised
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return;
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}
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2013-12-27 23:24:06 -04:00
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2014-02-10 20:22:08 -04:00
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uint16_t min_tx_buffer = 1024;
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2013-12-27 23:24:06 -04:00
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uint16_t min_rx_buffer = 512;
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if (strcmp(_devpath, "/dev/ttyACM0") == 0) {
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2013-12-28 01:01:48 -04:00
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min_tx_buffer = 16384;
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2013-12-27 23:24:06 -04:00
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min_rx_buffer = 1024;
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}
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2013-10-05 02:47:28 -03:00
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// on PX4 we have enough memory to have a larger transmit and
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// receive buffer for all ports. This means we don't get delays
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// while waiting to write GPS config packets
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2013-12-27 23:24:06 -04:00
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if (txS < min_tx_buffer) {
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txS = min_tx_buffer;
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2013-10-05 02:47:28 -03:00
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}
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2013-12-27 23:24:06 -04:00
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if (rxS < min_rx_buffer) {
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rxS = min_rx_buffer;
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2013-10-05 02:47:28 -03:00
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}
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2013-01-22 05:11:12 -04:00
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/*
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allocate the read buffer
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2013-10-05 02:47:28 -03:00
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we allocate buffers before we successfully open the device as we
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want to allocate in the early stages of boot, and cause minimum
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thrashing of the heap once we are up. The ttyACM0 driver may not
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connect for some time after boot
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2013-01-22 05:11:12 -04:00
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*/
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2013-01-21 19:34:04 -04:00
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if (rxS != 0 && rxS != _readbuf_size) {
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2013-10-05 02:47:28 -03:00
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_initialised = false;
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while (_in_timer) {
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hal.scheduler->delay(1);
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}
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2013-01-21 19:34:04 -04:00
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_readbuf_size = rxS;
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if (_readbuf != NULL) {
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free(_readbuf);
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}
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_readbuf = (uint8_t *)malloc(_readbuf_size);
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2013-01-22 05:11:12 -04:00
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_readbuf_head = 0;
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_readbuf_tail = 0;
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}
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2013-10-05 02:47:28 -03:00
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if (b != 0) {
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_baudrate = b;
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}
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2013-01-22 05:11:12 -04:00
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/*
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allocate the write buffer
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*/
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if (txS != 0 && txS != _writebuf_size) {
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2013-10-05 02:47:28 -03:00
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_initialised = false;
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while (_in_timer) {
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hal.scheduler->delay(1);
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}
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2013-01-22 05:11:12 -04:00
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_writebuf_size = txS;
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if (_writebuf != NULL) {
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free(_writebuf);
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}
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2013-02-20 03:15:56 -04:00
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_writebuf = (uint8_t *)malloc(_writebuf_size+16);
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2013-01-22 05:11:12 -04:00
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_writebuf_head = 0;
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_writebuf_tail = 0;
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2013-01-21 19:34:04 -04:00
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}
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2013-02-20 03:15:56 -04:00
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2013-10-05 02:47:28 -03:00
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if (_fd == -1) {
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_fd = open(_devpath, O_RDWR);
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if (_fd == -1) {
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return;
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}
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2014-02-10 20:22:08 -04:00
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// work out the OS write buffer size by looking at how many
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// bytes could be written when we first open the port
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int nwrite = 0;
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if (ioctl(_fd, FIONWRITE, (unsigned long)&nwrite) == 0) {
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_os_write_buffer_size = nwrite;
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if (_os_write_buffer_size & 1) {
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// it is reporting one short
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_os_write_buffer_size += 1;
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}
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}
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2013-10-05 02:47:28 -03:00
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}
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if (_baudrate != 0) {
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// set the baud rate
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struct termios t;
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tcgetattr(_fd, &t);
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cfsetspeed(&t, _baudrate);
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// disable LF -> CR/LF
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t.c_oflag &= ~ONLCR;
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tcsetattr(_fd, TCSANOW, &t);
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2014-02-12 02:47:23 -04:00
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// separately setup IFLOW if we can. We do this as a 2nd call
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// as if the port has no RTS pin then the tcsetattr() call
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// will fail, and if done as one call then it would fail to
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// set the baudrate.
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tcgetattr(_fd, &t);
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t.c_cflag |= CRTS_IFLOW;
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tcsetattr(_fd, TCSANOW, &t);
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2014-05-19 09:02:16 -03:00
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// reset _total_written to reset flow control auto check
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_total_written = 0;
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2013-10-05 02:47:28 -03:00
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}
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if (_writebuf_size != 0 && _readbuf_size != 0 && _fd != -1) {
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2013-10-12 22:43:25 -03:00
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if (!_initialised) {
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::printf("initialised %s OK %u %u\n", _devpath,
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(unsigned)_writebuf_size, (unsigned)_readbuf_size);
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}
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2013-02-20 03:15:56 -04:00
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_initialised = true;
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}
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2013-01-03 02:27:53 -04:00
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}
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2014-02-10 20:22:08 -04:00
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void PX4UARTDriver::set_flow_control(enum flow_control flow_control)
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2014-02-09 21:54:50 -04:00
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{
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if (_fd == -1) {
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return;
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}
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struct termios t;
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tcgetattr(_fd, &t);
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// we already enabled CRTS_IFLOW above, just enable output flow control
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2014-02-10 20:22:08 -04:00
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if (flow_control != FLOW_CONTROL_DISABLE) {
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2014-02-12 02:47:23 -04:00
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t.c_cflag |= CRTSCTS;
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2014-02-09 21:54:50 -04:00
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} else {
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2014-02-12 02:47:23 -04:00
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t.c_cflag &= ~CRTSCTS;
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2014-02-09 21:54:50 -04:00
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}
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tcsetattr(_fd, TCSANOW, &t);
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2014-02-10 20:22:08 -04:00
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_flow_control = flow_control;
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2014-02-09 21:54:50 -04:00
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}
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2013-01-04 04:42:30 -04:00
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void PX4UARTDriver::begin(uint32_t b)
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{
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2013-01-03 02:27:53 -04:00
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begin(b, 0, 0);
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}
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2013-10-05 02:47:28 -03:00
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/*
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try to initialise the UART. This is used to cope with the way NuttX
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handles /dev/ttyACM0 (the USB port). The port appears in /dev on
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boot, but cannot be opened until a USB cable is connected and the
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host starts the CDCACM communication.
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*/
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void PX4UARTDriver::try_initialise(void)
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{
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if (_initialised) {
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return;
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}
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if ((hal.scheduler->millis() - _last_initialise_attempt_ms) < 2000) {
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return;
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}
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_last_initialise_attempt_ms = hal.scheduler->millis();
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if (hal.util->safety_switch_state() != AP_HAL::Util::SAFETY_ARMED) {
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begin(0);
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}
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}
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2013-09-28 21:14:11 -03:00
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void PX4UARTDriver::end()
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{
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_initialised = false;
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while (_in_timer) hal.scheduler->delay(1);
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if (_fd != -1) {
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close(_fd);
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_fd = -1;
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}
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if (_readbuf) {
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free(_readbuf);
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_readbuf = NULL;
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}
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if (_writebuf) {
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free(_writebuf);
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_writebuf = NULL;
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}
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_readbuf_size = _writebuf_size = 0;
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_writebuf_head = 0;
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_writebuf_tail = 0;
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_readbuf_head = 0;
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_readbuf_tail = 0;
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}
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2013-01-02 20:03:05 -04:00
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void PX4UARTDriver::flush() {}
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2013-09-28 21:14:11 -03:00
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bool PX4UARTDriver::is_initialized()
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{
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2013-10-05 02:47:28 -03:00
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try_initialise();
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2013-09-28 21:14:11 -03:00
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return _initialised;
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}
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2013-01-21 19:50:26 -04:00
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void PX4UARTDriver::set_blocking_writes(bool blocking)
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{
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2013-01-22 06:52:21 -04:00
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_nonblocking_writes = !blocking;
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2013-01-03 06:12:10 -04:00
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}
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2013-09-28 21:14:11 -03:00
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2013-01-02 20:03:05 -04:00
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bool PX4UARTDriver::tx_pending() { return false; }
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2013-01-22 05:11:12 -04:00
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/*
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buffer handling macros
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*/
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#define BUF_AVAILABLE(buf) ((buf##_head > (_tail=buf##_tail))? (buf##_size - buf##_head) + _tail: _tail - buf##_head)
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2013-02-20 03:15:56 -04:00
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#define BUF_SPACE(buf) (((_head=buf##_head) > buf##_tail)?(_head - buf##_tail) - 1:((buf##_size - buf##_tail) + _head) - 1)
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2013-01-22 05:11:12 -04:00
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#define BUF_EMPTY(buf) (buf##_head == buf##_tail)
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#define BUF_ADVANCETAIL(buf, n) buf##_tail = (buf##_tail + n) % buf##_size
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#define BUF_ADVANCEHEAD(buf, n) buf##_head = (buf##_head + n) % buf##_size
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/*
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return number of bytes available to be read from the buffer
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*/
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int16_t PX4UARTDriver::available()
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{
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2013-01-03 06:12:10 -04:00
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if (!_initialised) {
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2013-10-05 02:47:28 -03:00
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try_initialise();
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2013-01-03 06:12:10 -04:00
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return 0;
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2013-01-03 02:27:53 -04:00
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}
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2013-01-22 05:11:12 -04:00
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uint16_t _tail;
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return BUF_AVAILABLE(_readbuf);
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2013-01-03 02:27:53 -04:00
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}
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2013-01-22 05:11:12 -04:00
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/*
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return number of bytes that can be added to the write buffer
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*/
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int16_t PX4UARTDriver::txspace()
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{
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2013-01-03 06:12:10 -04:00
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if (!_initialised) {
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2013-10-05 02:47:28 -03:00
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try_initialise();
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2013-01-03 06:12:10 -04:00
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return 0;
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}
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2013-01-22 05:11:12 -04:00
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uint16_t _head;
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return BUF_SPACE(_writebuf);
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2013-01-03 02:27:53 -04:00
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}
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2013-01-02 20:03:05 -04:00
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2013-01-22 05:11:12 -04:00
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/*
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read one byte from the read buffer
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*/
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int16_t PX4UARTDriver::read()
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{
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2013-01-21 19:34:04 -04:00
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uint8_t c;
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2013-10-05 02:47:28 -03:00
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if (!_initialised) {
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try_initialise();
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return -1;
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}
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if (_readbuf == NULL) {
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2013-01-21 19:34:04 -04:00
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return -1;
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}
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2013-01-22 05:11:12 -04:00
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if (BUF_EMPTY(_readbuf)) {
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return -1;
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}
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c = _readbuf[_readbuf_head];
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BUF_ADVANCEHEAD(_readbuf, 1);
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2013-01-21 19:34:04 -04:00
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return c;
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2013-01-02 20:03:05 -04:00
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}
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2013-01-22 05:11:12 -04:00
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/*
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write one byte to the buffer
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*/
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2013-01-21 19:50:26 -04:00
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size_t PX4UARTDriver::write(uint8_t c)
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{
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2013-01-22 06:52:21 -04:00
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if (!_initialised) {
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2013-10-05 02:47:28 -03:00
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try_initialise();
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2013-01-22 05:11:12 -04:00
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return 0;
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2013-01-21 19:50:26 -04:00
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}
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2013-01-22 18:22:51 -04:00
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if (hal.scheduler->in_timerprocess()) {
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// not allowed from timers
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return 0;
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}
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2013-01-22 06:52:21 -04:00
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uint16_t _head;
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2013-02-18 21:02:46 -04:00
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2013-01-22 06:52:21 -04:00
|
|
|
while (BUF_SPACE(_writebuf) == 0) {
|
|
|
|
if (_nonblocking_writes) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
hal.scheduler->delay(1);
|
|
|
|
}
|
2013-01-22 05:11:12 -04:00
|
|
|
_writebuf[_writebuf_tail] = c;
|
|
|
|
BUF_ADVANCETAIL(_writebuf, 1);
|
|
|
|
return 1;
|
2013-01-21 19:50:26 -04:00
|
|
|
}
|
|
|
|
|
2013-01-22 05:11:12 -04:00
|
|
|
/*
|
|
|
|
write size bytes to the write buffer
|
|
|
|
*/
|
2013-01-21 19:50:26 -04:00
|
|
|
size_t PX4UARTDriver::write(const uint8_t *buffer, size_t size)
|
|
|
|
{
|
|
|
|
if (!_initialised) {
|
2013-10-05 02:47:28 -03:00
|
|
|
try_initialise();
|
2013-01-03 06:12:10 -04:00
|
|
|
return 0;
|
|
|
|
}
|
2013-01-22 18:22:51 -04:00
|
|
|
if (hal.scheduler->in_timerprocess()) {
|
|
|
|
// not allowed from timers
|
|
|
|
return 0;
|
|
|
|
}
|
2013-03-20 01:41:52 -03:00
|
|
|
|
|
|
|
if (!_nonblocking_writes) {
|
|
|
|
/*
|
|
|
|
use the per-byte delay loop in write() above for blocking writes
|
|
|
|
*/
|
|
|
|
size_t ret = 0;
|
|
|
|
while (size--) {
|
|
|
|
if (write(*buffer++) != 1) break;
|
|
|
|
ret++;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-01-22 05:11:12 -04:00
|
|
|
uint16_t _head, space;
|
|
|
|
space = BUF_SPACE(_writebuf);
|
|
|
|
if (space == 0) {
|
|
|
|
return 0;
|
2013-01-21 19:50:26 -04:00
|
|
|
}
|
2013-01-22 05:11:12 -04:00
|
|
|
if (size > space) {
|
|
|
|
size = space;
|
|
|
|
}
|
|
|
|
if (_writebuf_tail < _head) {
|
|
|
|
// perform as single memcpy
|
2013-02-20 03:15:56 -04:00
|
|
|
assert(_writebuf_tail+size <= _writebuf_size);
|
2013-01-22 05:11:12 -04:00
|
|
|
memcpy(&_writebuf[_writebuf_tail], buffer, size);
|
|
|
|
BUF_ADVANCETAIL(_writebuf, size);
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
|
|
|
// perform as two memcpy calls
|
|
|
|
uint16_t n = _writebuf_size - _writebuf_tail;
|
|
|
|
if (n > size) n = size;
|
2013-02-20 03:15:56 -04:00
|
|
|
assert(_writebuf_tail+n <= _writebuf_size);
|
2013-01-22 05:11:12 -04:00
|
|
|
memcpy(&_writebuf[_writebuf_tail], buffer, n);
|
|
|
|
BUF_ADVANCETAIL(_writebuf, n);
|
|
|
|
buffer += n;
|
|
|
|
n = size - n;
|
|
|
|
if (n > 0) {
|
2013-02-20 03:15:56 -04:00
|
|
|
assert(_writebuf_tail+n <= _writebuf_size);
|
2013-01-22 05:11:12 -04:00
|
|
|
memcpy(&_writebuf[_writebuf_tail], buffer, n);
|
|
|
|
BUF_ADVANCETAIL(_writebuf, n);
|
|
|
|
}
|
|
|
|
return size;
|
2013-01-02 22:16:41 -04:00
|
|
|
}
|
|
|
|
|
2013-02-18 21:02:46 -04:00
|
|
|
/*
|
|
|
|
try writing n bytes, handling an unresponsive port
|
|
|
|
*/
|
|
|
|
int PX4UARTDriver::_write_fd(const uint8_t *buf, uint16_t n)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
// the FIONWRITE check is to cope with broken O_NONBLOCK behaviour
|
|
|
|
// in NuttX on ttyACM0
|
|
|
|
int nwrite = 0;
|
2014-02-10 20:22:08 -04:00
|
|
|
|
2013-02-18 21:02:46 -04:00
|
|
|
if (ioctl(_fd, FIONWRITE, (unsigned long)&nwrite) == 0) {
|
2014-02-10 20:22:08 -04:00
|
|
|
if (nwrite == 0 &&
|
|
|
|
_flow_control == FLOW_CONTROL_AUTO &&
|
|
|
|
_last_write_time != 0 &&
|
|
|
|
_total_written != 0 &&
|
|
|
|
_os_write_buffer_size == _total_written &&
|
2014-08-19 19:41:57 -03:00
|
|
|
(hal.scheduler->micros64() - _last_write_time) > 500*1000UL) {
|
2014-02-10 20:22:08 -04:00
|
|
|
// it doesn't look like hw flow control is working
|
|
|
|
::printf("disabling flow control on %s _total_written=%u\n",
|
|
|
|
_devpath, (unsigned)_total_written);
|
|
|
|
set_flow_control(FLOW_CONTROL_DISABLE);
|
|
|
|
}
|
2013-02-18 21:02:46 -04:00
|
|
|
if (nwrite > n) {
|
|
|
|
nwrite = n;
|
|
|
|
}
|
|
|
|
if (nwrite > 0) {
|
|
|
|
ret = ::write(_fd, buf, nwrite);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ret > 0) {
|
|
|
|
BUF_ADVANCEHEAD(_writebuf, ret);
|
2014-08-19 19:41:57 -03:00
|
|
|
_last_write_time = hal.scheduler->micros64();
|
2014-02-10 20:22:08 -04:00
|
|
|
_total_written += ret;
|
2013-02-18 21:02:46 -04:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-08-19 19:41:57 -03:00
|
|
|
if (hal.scheduler->micros64() - _last_write_time > 2000 &&
|
2014-02-10 20:22:08 -04:00
|
|
|
_flow_control == FLOW_CONTROL_DISABLE) {
|
2013-03-19 21:02:28 -03:00
|
|
|
#if 0
|
|
|
|
// this trick is disabled for now, as it sometimes blocks on
|
|
|
|
// re-opening the ttyACM0 port, which would cause a crash
|
2014-08-19 19:41:57 -03:00
|
|
|
if (hal.scheduler->micros64() - _last_write_time > 2000000) {
|
2013-03-19 21:02:28 -03:00
|
|
|
// we haven't done a successful write for 2 seconds - try
|
|
|
|
// reopening the port
|
|
|
|
_initialised = false;
|
|
|
|
::close(_fd);
|
2013-03-20 01:41:52 -03:00
|
|
|
_fd = ::open(_devpath, O_RDWR);
|
2013-03-19 21:02:28 -03:00
|
|
|
if (_fd == -1) {
|
|
|
|
fprintf(stdout, "Failed to reopen UART device %s - %s\n",
|
|
|
|
_devpath, strerror(errno));
|
|
|
|
// leave it uninitialised
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
|
2014-08-19 19:41:57 -03:00
|
|
|
_last_write_time = hal.scheduler->micros64();
|
2013-03-19 21:02:28 -03:00
|
|
|
_initialised = true;
|
|
|
|
}
|
|
|
|
#else
|
2014-08-19 19:41:57 -03:00
|
|
|
_last_write_time = hal.scheduler->micros64();
|
2013-03-19 21:02:28 -03:00
|
|
|
#endif
|
|
|
|
// we haven't done a successful write for 2ms, which means the
|
2013-02-18 21:02:46 -04:00
|
|
|
// port is running at less than 500 bytes/sec. Start
|
|
|
|
// discarding bytes, even if this is a blocking port. This
|
|
|
|
// prevents the ttyACM0 port blocking startup if the endpoint
|
|
|
|
// is not connected
|
|
|
|
BUF_ADVANCEHEAD(_writebuf, n);
|
|
|
|
return n;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-03-20 01:41:52 -03:00
|
|
|
/*
|
|
|
|
try reading n bytes, handling an unresponsive port
|
|
|
|
*/
|
|
|
|
int PX4UARTDriver::_read_fd(uint8_t *buf, uint16_t n)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
// the FIONREAD check is to cope with broken O_NONBLOCK behaviour
|
|
|
|
// in NuttX on ttyACM0
|
|
|
|
int nread = 0;
|
|
|
|
if (ioctl(_fd, FIONREAD, (unsigned long)&nread) == 0) {
|
|
|
|
if (nread > n) {
|
|
|
|
nread = n;
|
|
|
|
}
|
|
|
|
if (nread > 0) {
|
|
|
|
ret = ::read(_fd, buf, nread);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (ret > 0) {
|
|
|
|
BUF_ADVANCETAIL(_readbuf, ret);
|
2014-02-10 20:22:08 -04:00
|
|
|
_total_read += ret;
|
2013-03-20 01:41:52 -03:00
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-01-22 05:11:12 -04:00
|
|
|
/*
|
|
|
|
push any pending bytes to/from the serial port. This is called at
|
|
|
|
1kHz in the timer thread. Doing it this way reduces the system call
|
|
|
|
overhead in the main task enormously.
|
|
|
|
*/
|
|
|
|
void PX4UARTDriver::_timer_tick(void)
|
2013-01-04 17:09:23 -04:00
|
|
|
{
|
2013-01-22 05:11:12 -04:00
|
|
|
uint16_t n;
|
|
|
|
|
|
|
|
if (!_initialised) return;
|
|
|
|
|
2013-11-04 23:41:42 -04:00
|
|
|
// don't try IO on a disconnected USB port
|
|
|
|
if (strcmp(_devpath, "/dev/ttyACM0") == 0 && !hal.gpio->usb_connected()) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-01-22 05:11:12 -04:00
|
|
|
_in_timer = true;
|
|
|
|
|
|
|
|
// write any pending bytes
|
|
|
|
uint16_t _tail;
|
|
|
|
n = BUF_AVAILABLE(_writebuf);
|
|
|
|
if (n > 0) {
|
2013-01-24 00:01:48 -04:00
|
|
|
perf_begin(_perf_uart);
|
2013-01-22 05:11:12 -04:00
|
|
|
if (_tail > _writebuf_head) {
|
|
|
|
// do as a single write
|
2013-02-18 21:02:46 -04:00
|
|
|
_write_fd(&_writebuf[_writebuf_head], n);
|
2013-01-22 05:11:12 -04:00
|
|
|
} else {
|
|
|
|
// split into two writes
|
|
|
|
uint16_t n1 = _writebuf_size - _writebuf_head;
|
2013-02-18 21:02:46 -04:00
|
|
|
int ret = _write_fd(&_writebuf[_writebuf_head], n1);
|
2014-08-18 20:30:08 -03:00
|
|
|
if (ret == n1 && n > n1) {
|
2013-02-18 21:02:46 -04:00
|
|
|
_write_fd(&_writebuf[_writebuf_head], n - n1);
|
2013-01-22 05:11:12 -04:00
|
|
|
}
|
|
|
|
}
|
2013-01-24 00:01:48 -04:00
|
|
|
perf_end(_perf_uart);
|
2013-01-22 05:11:12 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
// try to fill the read buffer
|
|
|
|
uint16_t _head;
|
|
|
|
n = BUF_SPACE(_readbuf);
|
|
|
|
if (n > 0) {
|
2013-01-24 00:01:48 -04:00
|
|
|
perf_begin(_perf_uart);
|
2013-01-22 05:11:12 -04:00
|
|
|
if (_readbuf_tail < _head) {
|
|
|
|
// one read will do
|
2013-02-20 03:15:56 -04:00
|
|
|
assert(_readbuf_tail+n <= _readbuf_size);
|
2013-03-20 01:41:52 -03:00
|
|
|
_read_fd(&_readbuf[_readbuf_tail], n);
|
2013-01-22 05:11:12 -04:00
|
|
|
} else {
|
|
|
|
uint16_t n1 = _readbuf_size - _readbuf_tail;
|
2013-02-20 03:15:56 -04:00
|
|
|
assert(_readbuf_tail+n1 <= _readbuf_size);
|
2013-03-20 01:41:52 -03:00
|
|
|
int ret = _read_fd(&_readbuf[_readbuf_tail], n1);
|
2014-08-18 20:30:08 -03:00
|
|
|
if (ret == n1 && n > n1) {
|
2013-02-20 03:15:56 -04:00
|
|
|
assert(_readbuf_tail+(n-n1) <= _readbuf_size);
|
2013-03-20 01:41:52 -03:00
|
|
|
_read_fd(&_readbuf[_readbuf_tail], n - n1);
|
2013-01-22 05:11:12 -04:00
|
|
|
}
|
|
|
|
}
|
2013-01-24 00:01:48 -04:00
|
|
|
perf_end(_perf_uart);
|
2013-01-22 05:11:12 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
_in_timer = false;
|
2013-01-04 17:09:23 -04:00
|
|
|
}
|
|
|
|
|
2013-01-04 17:01:10 -04:00
|
|
|
#endif // CONFIG_HAL_BOARD
|
2013-01-02 20:03:05 -04:00
|
|
|
|