2014-11-13 23:10:35 -04:00
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2015-08-11 03:28:43 -03:00
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#include <AP_HAL/AP_HAL.h>
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2014-11-13 23:10:35 -04:00
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#include "RCOutput_ZYNQ.h"
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2016-05-17 23:26:57 -03:00
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2014-11-13 23:10:35 -04:00
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#include <dirent.h>
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2016-05-17 23:26:57 -03:00
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#include <fcntl.h>
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#include <linux/spi/spidev.h>
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#include <signal.h>
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2014-11-13 23:10:35 -04:00
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#include <stdint.h>
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2016-05-17 23:26:57 -03:00
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#include <stdio.h>
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#include <stdlib.h>
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2014-11-13 23:10:35 -04:00
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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2016-05-17 23:26:57 -03:00
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#include <sys/stat.h>
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#include <sys/types.h>
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#include <unistd.h>
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2014-11-13 23:10:35 -04:00
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using namespace Linux;
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2016-07-29 20:26:07 -03:00
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#define PWM_CHAN_COUNT 8
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#define RCOUT_ZYNQ_PWM_BASE 0x43c00000
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#define PWM_CMD_CONFIG 0 /* full configuration in one go */
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#define PWM_CMD_ENABLE 1 /* enable a pwm */
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#define PWM_CMD_DISABLE 2 /* disable a pwm */
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#define PWM_CMD_MODIFY 3 /* modify a pwm */
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#define PWM_CMD_SET 4 /* set a pwm output explicitly */
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#define PWM_CMD_CLR 5 /* clr a pwm output explicitly */
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#define PWM_CMD_TEST 6 /* various crap */
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2014-11-13 23:10:35 -04:00
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static void catch_sigbus(int sig)
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{
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2024-12-13 05:15:44 -04:00
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AP_HAL::panic("RCOutput.cpp:SIGBUS error generated");
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2014-11-13 23:10:35 -04:00
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}
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2015-12-02 11:14:20 -04:00
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void RCOutput_ZYNQ::init()
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2014-11-13 23:10:35 -04:00
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{
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uint32_t mem_fd;
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signal(SIGBUS,catch_sigbus);
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2016-10-30 10:22:29 -03:00
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mem_fd = open("/dev/mem", O_RDWR|O_SYNC|O_CLOEXEC);
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2014-11-13 23:10:35 -04:00
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sharedMem_cmd = (struct pwm_cmd *) mmap(0, 0x1000, PROT_READ|PROT_WRITE,
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MAP_SHARED, mem_fd, RCOUT_ZYNQ_PWM_BASE);
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close(mem_fd);
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// all outputs default to 50Hz, the top level vehicle code
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// overrides this when necessary
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set_freq(0xFFFFFFFF, 50);
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}
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2015-10-20 18:13:25 -03:00
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void RCOutput_ZYNQ::set_freq(uint32_t chmask, uint16_t freq_hz) //LSB corresponds to CHAN_1
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2014-11-13 23:10:35 -04:00
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{
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uint8_t i;
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unsigned long tick=TICK_PER_S/(unsigned long)freq_hz;
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for (i=0;i<PWM_CHAN_COUNT;i++) {
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if (chmask & (1U<<i)) {
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sharedMem_cmd->periodhi[i].period=tick;
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}
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}
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}
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2015-10-20 18:13:25 -03:00
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uint16_t RCOutput_ZYNQ::get_freq(uint8_t ch)
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2014-11-13 23:10:35 -04:00
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{
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2017-04-05 12:05:10 -03:00
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if (ch >= PWM_CHAN_COUNT) {
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return 0;
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}
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return TICK_PER_S/sharedMem_cmd->periodhi[ch].period;
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2014-11-13 23:10:35 -04:00
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}
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2015-10-20 18:13:25 -03:00
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void RCOutput_ZYNQ::enable_ch(uint8_t ch)
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2014-11-13 23:10:35 -04:00
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{
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// sharedMem_cmd->enmask |= 1U<<chan_pru_map[ch];
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}
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2015-10-20 18:13:25 -03:00
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void RCOutput_ZYNQ::disable_ch(uint8_t ch)
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2014-11-13 23:10:35 -04:00
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{
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// sharedMem_cmd->enmask &= !(1U<<chan_pru_map[ch]);
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}
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2015-10-20 18:13:25 -03:00
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void RCOutput_ZYNQ::write(uint8_t ch, uint16_t period_us)
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2014-11-13 23:10:35 -04:00
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{
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2017-04-05 12:05:10 -03:00
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if (ch >= PWM_CHAN_COUNT) {
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return;
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}
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2016-10-11 21:19:16 -03:00
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if (corked) {
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pending[ch] = period_us;
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pending_mask |= (1U << ch);
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} else {
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sharedMem_cmd->periodhi[ch].hi = TICK_PER_US*period_us;
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}
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2014-11-13 23:10:35 -04:00
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}
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2015-10-20 18:13:25 -03:00
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uint16_t RCOutput_ZYNQ::read(uint8_t ch)
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2014-11-13 23:10:35 -04:00
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{
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2017-04-05 12:05:10 -03:00
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if (ch >= PWM_CHAN_COUNT) {
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return 0;
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}
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return sharedMem_cmd->periodhi[ch].hi/TICK_PER_US;
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2014-11-13 23:10:35 -04:00
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}
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2015-10-20 18:13:25 -03:00
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void RCOutput_ZYNQ::read(uint16_t* period_us, uint8_t len)
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2014-11-13 23:10:35 -04:00
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{
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uint8_t i;
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if(len>PWM_CHAN_COUNT){
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len = PWM_CHAN_COUNT;
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}
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for(i=0;i<len;i++){
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period_us[i] = sharedMem_cmd->periodhi[i].hi/TICK_PER_US;
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}
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}
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2016-10-11 21:19:16 -03:00
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void RCOutput_ZYNQ::cork(void)
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{
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corked = true;
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}
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void RCOutput_ZYNQ::push(void)
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{
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2017-04-17 21:01:54 -03:00
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if (!corked) {
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return;
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}
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2016-10-11 21:19:16 -03:00
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corked = false;
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for (uint8_t i=0; i<MAX_ZYNQ_PWMS; i++) {
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if (pending_mask & (1U << i)) {
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write(i, pending[i]);
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}
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}
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pending_mask = 0;
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}
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