2018-01-05 02:19:51 -04:00
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/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Code by Andrew Tridgell and Siddharth Bharat Purohit
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <AP_HAL/AP_HAL.h>
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#include <AP_HAL/system.h>
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#include <ch.h>
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#include "hal.h"
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#include <hrt.h>
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extern const AP_HAL::HAL& hal;
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extern "C"
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{
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#define bkpt() __asm volatile("BKPT #0\n")
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typedef enum {
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Reset = 1,
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NMI = 2,
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HardFault = 3,
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MemManage = 4,
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BusFault = 5,
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UsageFault = 6,
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} FaultType;
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void *__dso_handle;
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2018-02-07 01:46:13 -04:00
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void __cxa_pure_virtual(void);
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2018-01-05 02:19:51 -04:00
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void __cxa_pure_virtual() { while (1); } //TODO: Handle properly, maybe generate a traceback
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2018-02-07 01:46:13 -04:00
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void NMI_Handler(void);
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2018-01-05 02:19:51 -04:00
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void NMI_Handler(void) { while (1); }
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2018-02-07 01:46:13 -04:00
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void HardFault_Handler(void);
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2018-01-05 02:19:51 -04:00
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void HardFault_Handler(void) {
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//Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info
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//Get thread context. Contains main registers including PC and LR
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struct port_extctx ctx;
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memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx));
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(void)ctx;
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//Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
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FaultType faultType = (FaultType)__get_IPSR();
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(void)faultType;
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//For HardFault/BusFault this is the address that was accessed causing the error
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uint32_t faultAddress = SCB->BFAR;
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(void)faultAddress;
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//Flags about hardfault / busfault
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//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
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bool isFaultPrecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 1) ? true : false);
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bool isFaultImprecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 2) ? true : false);
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bool isFaultOnUnstacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 3) ? true : false);
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bool isFaultOnStacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 4) ? true : false);
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bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 7) ? true : false);
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(void)isFaultPrecise;
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(void)isFaultImprecise;
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(void)isFaultOnUnstacking;
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(void)isFaultOnStacking;
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(void)isFaultAddressValid;
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//Cause debugger to stop. Ignored if no debugger is attached
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while(1) {}
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}
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void BusFault_Handler(void) __attribute__((alias("HardFault_Handler")));
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2018-02-07 01:46:13 -04:00
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void UsageFault_Handler(void);
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2018-01-05 02:19:51 -04:00
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void UsageFault_Handler(void) {
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//Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info
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//Get thread context. Contains main registers including PC and LR
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struct port_extctx ctx;
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memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx));
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(void)ctx;
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//Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
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FaultType faultType = (FaultType)__get_IPSR();
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(void)faultType;
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//Flags about hardfault / busfault
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//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
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bool isUndefinedInstructionFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 0) ? true : false);
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bool isEPSRUsageFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 1) ? true : false);
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bool isInvalidPCFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 2) ? true : false);
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bool isNoCoprocessorFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 3) ? true : false);
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bool isUnalignedAccessFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 8) ? true : false);
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bool isDivideByZeroFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 9) ? true : false);
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(void)isUndefinedInstructionFault;
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(void)isEPSRUsageFault;
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(void)isInvalidPCFault;
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(void)isNoCoprocessorFault;
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(void)isUnalignedAccessFault;
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(void)isDivideByZeroFault;
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//Cause debugger to stop. Ignored if no debugger is attached
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while(1) {}
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}
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2018-02-07 01:46:13 -04:00
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void MemManage_Handler(void);
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2018-01-05 02:19:51 -04:00
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void MemManage_Handler(void) {
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//Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info
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//Get thread context. Contains main registers including PC and LR
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struct port_extctx ctx;
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memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx));
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(void)ctx;
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//Interrupt status register: Which interrupt have we encountered, e.g. HardFault?
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FaultType faultType = (FaultType)__get_IPSR();
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(void)faultType;
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//For HardFault/BusFault this is the address that was accessed causing the error
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uint32_t faultAddress = SCB->MMFAR;
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(void)faultAddress;
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//Flags about hardfault / busfault
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//See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference
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bool isInstructionAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 0) ? true : false);
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bool isDataAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 1) ? true : false);
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bool isExceptionUnstackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 3) ? true : false);
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bool isExceptionStackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 4) ? true : false);
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bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 7) ? true : false);
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(void)isInstructionAccessViolation;
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(void)isDataAccessViolation;
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(void)isExceptionUnstackingFault;
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(void)isExceptionStackingFault;
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(void)isFaultAddressValid;
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while(1) {}
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}
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}
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namespace AP_HAL {
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void init()
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{
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}
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void panic(const char *errormsg, ...)
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{
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va_list ap;
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va_start(ap, errormsg);
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vprintf(errormsg, ap);
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va_end(ap);
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hal.scheduler->delay_microseconds(10000);
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while(1) {}
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}
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uint32_t micros()
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{
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return hrt_micros32();
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}
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uint32_t millis()
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{
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return hrt_millis32();
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}
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uint64_t micros64()
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{
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2018-08-08 03:57:05 -03:00
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return hrt_micros64();
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2018-01-05 02:19:51 -04:00
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}
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uint64_t millis64()
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{
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2018-08-08 03:57:05 -03:00
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return hrt_micros64() / 1000U;
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2018-01-05 02:19:51 -04:00
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}
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} // namespace AP_HAL
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