2018-01-17 15:29:06 -04:00
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/*
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* This file is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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2019-10-20 10:31:12 -03:00
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*
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2018-01-17 15:29:06 -04:00
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* Code by Andrew Tridgell and Siddharth Bharat Purohit
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*/
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#include "SoftSigReader.h"
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2018-04-25 20:10:27 -03:00
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#include "hwdef/common/stm32_util.h"
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2018-01-17 15:29:06 -04:00
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#if CONFIG_HAL_BOARD == HAL_BOARD_CHIBIOS
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using namespace ChibiOS;
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extern const AP_HAL::HAL& hal;
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2018-01-17 19:54:37 -04:00
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#if HAL_USE_ICU == TRUE
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2018-01-17 15:29:06 -04:00
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bool SoftSigReader::attach_capture_timer(ICUDriver* icu_drv, icuchannel_t chan, uint8_t dma_stream, uint32_t dma_channel)
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{
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if (chan > ICU_CHANNEL_2) {
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return false;
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}
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2018-11-03 02:46:02 -03:00
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signal = (uint32_t*)hal.util->malloc_type(sizeof(uint32_t)*SOFTSIG_BOUNCE_BUF_SIZE, AP_HAL::Util::MEM_DMA_SAFE);
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2018-01-17 15:29:06 -04:00
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if (signal == nullptr) {
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return false;
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}
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2018-01-18 15:13:52 -04:00
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_icu_drv = icu_drv;
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2018-01-17 15:29:06 -04:00
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//Setup Burst transfer of period and width measurement
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2019-02-01 21:47:46 -04:00
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osalDbgAssert(dma == nullptr, "double DMA allocation");
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2018-02-05 17:14:02 -04:00
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chSysLock();
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2019-02-01 21:47:46 -04:00
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dma = dmaStreamAllocI(dma_stream,
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12, //IRQ Priority
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(stm32_dmaisr_t)_irq_handler,
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(void *)this);
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osalDbgAssert(dma, "stream allocation failed");
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2018-02-05 17:14:02 -04:00
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chSysUnlock();
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2019-02-13 16:10:55 -04:00
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#if STM32_DMA_SUPPORTS_DMAMUX
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dmaSetRequestSource(dma, dma_channel);
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#endif
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2018-01-17 15:29:06 -04:00
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//setup address for full word transfer from Timer
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dmaStreamSetPeripheral(dma, &icu_drv->tim->DMAR);
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2018-10-05 21:32:54 -03:00
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dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
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2018-01-17 15:29:06 -04:00
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dmamode |= STM32_DMA_CR_CHSEL(dma_channel);
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dmamode |= STM32_DMA_CR_PL(0);
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2018-10-05 21:32:54 -03:00
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dmamode |= STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_PSIZE_WORD |
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STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE;
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2018-01-17 15:29:06 -04:00
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dmaStreamSetMemory0(dma, signal);
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2018-11-03 02:46:02 -03:00
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dmaStreamSetTransactionSize(dma, SOFTSIG_BOUNCE_BUF_SIZE);
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2018-10-05 21:32:54 -03:00
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dmaStreamSetMode(dma, dmamode);
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2018-01-17 15:29:06 -04:00
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icucfg.frequency = INPUT_CAPTURE_FREQUENCY;
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icucfg.channel = chan;
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icucfg.width_cb = NULL;
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icucfg.period_cb = NULL;
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icucfg.overflow_cb = NULL;
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if (chan == ICU_CHANNEL_1) {
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icucfg.dier = STM32_TIM_DIER_CC1DE;
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2018-01-18 15:13:52 -04:00
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icucfg.mode = ICU_INPUT_ACTIVE_HIGH;
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need_swap = true;
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2018-01-17 15:29:06 -04:00
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} else {
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2018-01-18 15:13:52 -04:00
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icucfg.mode = ICU_INPUT_ACTIVE_LOW;
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2018-01-17 15:29:06 -04:00
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icucfg.dier = STM32_TIM_DIER_CC2DE;
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}
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2018-02-11 21:12:00 -04:00
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#ifdef HAL_RCIN_IS_INVERTED
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icucfg.mode = (icucfg.mode==ICU_INPUT_ACTIVE_LOW)?ICU_INPUT_ACTIVE_HIGH:ICU_INPUT_ACTIVE_LOW;
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#endif
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2018-01-18 15:13:52 -04:00
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icuStart(_icu_drv, &icucfg);
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2018-01-17 15:29:06 -04:00
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//Extended Timer Setup to enable DMA transfer
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//selected offset for TIM_CCR1 and for two words
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2018-01-18 15:13:52 -04:00
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_icu_drv->tim->DCR = STM32_TIM_DCR_DBA(0x0D) | STM32_TIM_DCR_DBL(1);
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2018-01-17 15:29:06 -04:00
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//Enable DMA
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dmaStreamEnable(dma);
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2018-04-25 20:10:27 -03:00
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//sets input filtering to 4 timer clock
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stm32_timer_set_input_filter(_icu_drv->tim, chan, 2);
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2018-01-17 15:29:06 -04:00
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//Start Timer
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2018-01-18 15:13:52 -04:00
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icuStartCapture(_icu_drv);
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2018-01-17 15:29:06 -04:00
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return true;
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}
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void SoftSigReader::_irq_handler(void* self, uint32_t flags)
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{
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SoftSigReader* sig_reader = (SoftSigReader*)self;
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2018-11-03 02:46:02 -03:00
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// we need to restart the DMA as quickly as possible to prevent losing pulses, so we
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// make a fixed length copy to a 2nd buffer. On the F100 this reduces the time with DMA
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// disabled from 20us to under 1us
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2019-08-02 07:57:01 -03:00
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stm32_cacheBufferInvalidate(sig_reader->signal, SOFTSIG_BOUNCE_BUF_SIZE*4);
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2018-11-03 02:46:02 -03:00
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memcpy(sig_reader->signal2, sig_reader->signal, SOFTSIG_BOUNCE_BUF_SIZE*4);
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2018-01-17 15:29:06 -04:00
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//restart the DMA transfers
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2018-10-05 21:32:54 -03:00
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dmaStreamDisable(sig_reader->dma);
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dmaStreamSetPeripheral(sig_reader->dma, &sig_reader->_icu_drv->tim->DMAR);
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2018-01-17 15:29:06 -04:00
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dmaStreamSetMemory0(sig_reader->dma, sig_reader->signal);
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2018-11-03 02:46:02 -03:00
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dmaStreamSetTransactionSize(sig_reader->dma, SOFTSIG_BOUNCE_BUF_SIZE);
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2018-10-05 21:32:54 -03:00
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dmaStreamSetMode(sig_reader->dma, sig_reader->dmamode);
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2018-01-17 15:29:06 -04:00
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dmaStreamEnable(sig_reader->dma);
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2018-11-05 07:02:06 -04:00
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sig_reader->sigbuf.push((const pulse_t *)sig_reader->signal2, SOFTSIG_BOUNCE_BUF_SIZE/2);
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2018-01-17 15:29:06 -04:00
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}
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2018-01-17 19:54:37 -04:00
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#endif // HAL_USE_ICU
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2018-01-17 15:29:06 -04:00
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2018-01-17 18:04:42 -04:00
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#endif //CONFIG_HAL_BOARD == HAL_BOARD_CHIBIOS
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