/*
 * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include "dt-bindings/interrupt-controller/tegra-t19x-agic.h"

/ {
	sound {
		iommus = <&smmu TEGRA_SID_APE>;
		dma-mask = <0x0 0x5e000000>;
		iommu-resv-regions = <0x0 0x0 0x0 0x40000000 0x0 0x60000000 0xffffffff 0xffffffff>;
		iommu-group-id = <TEGRA_IOMMU_GROUP_APE>;
		status = "disabled";
	};

	sound_ref {
		iommus = <&smmu TEGRA_SID_APE>;
		dma-mask = <0x0 0x5e000000>;
		iommu-resv-regions = <0x0 0x0 0x0 0x40000000 0x0 0x60000000 0xffffffff 0xffffffff>;
		iommu-group-id = <TEGRA_IOMMU_GROUP_APE>;
		status = "disabled";
	};

	aconnect@2a41000 {
		compatible = "nvidia,tegra210-aconnect";
		clocks = <&bpmp_clks TEGRA194_CLK_APE>,
			 <&bpmp_clks TEGRA194_CLK_APB2APE>;
		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
		clock-names = "ape", "apb2ape";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		tegra_agic: agic-controller@2a41000 {
			compatible = "nvidia,tegra186-agic";
			#interrupt-cells = <4>;
			interrupt-controller;
			reg = <0x0 0x02a41000 0x0 0x1000>,
				<0x0 0x02a42000 0x0 0x1000>;
			interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&bpmp_clks TEGRA194_CLK_APE>;
			clock-names = "clk";
			status = "disabled";
		};

		tegra_agic_1: agic-controller@2a51000 {
			compatible = "nvidia,tegra186-agic";
			interrupt-controller;
			#interrupt-cells = <4>;
			reg = <0x0 0x02a51000 0x0 0x1000>,
				<0x0 0x02a52000 0x0 0x1000>;
			interrupts = <GIC_SPI 146 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&bpmp_clks TEGRA194_CLK_APE>;
			clock-names = "clk";
			status = "disabled";
		};

		tegra_agic_2: agic-controller@2a61000 {
			compatible = "nvidia,tegra186-agic";
			interrupt-controller;
			#interrupt-cells = <4>;
			reg = <0x0 0x02a61000 0x0 0x1000>,
				<0x0 0x02a62000 0x0 0x1000>;
			interrupts = <GIC_SPI 147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&bpmp_clks TEGRA194_CLK_APE>;
			clock-names = "clk";
			status = "disabled";
		};

		adsp@2993000 {
			compatible = "nvidia,tegra18x-adsp";
			interrupt-parent = <&tegra_agic>;
			nvidia,adsp_os_secload;
			reg = <0x0 0x02993000 0x0 0x1000>, /* AMC */
				<0x0 0x02990000 0x0 0x2000>, /* AMISC */
				<0x0 0x0 0x0 0x1>, /* ABRIDGE */
				<0x0 0x0290C800 0x0 0x1>, /* FPGA RESET REG */
				<0x0 0x029B0000 0x0 0x90000>, /* AHSP */
				<0x0 0x40000000 0x0 0xC0000000>, /* DRAM MAP1 */
				<0x0 0x0 0x0 0x1>; /* DRAM MAP2 */
			nvidia,adsp_mem = <0x5EF00000 0x01000000>, /* ADSP OS */
				<0x5F700000 0x00800000>, /* ADSP APP */
				<0x3F813000 0x5000>, /* ARAM ALIAS 0 */
				<0x5FD00000 0x200000>; /* ACSR */
			nvidia,adsp-evp-base = <0x02993700 0x00000040>;
			interrupts = <GIC_SPI INT_AMISC_MBOX_EMPTY1 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_HOST_INTF0>, /* MBOX SEND */
				     <GIC_SPI INT_AMISC_MBOX_FULL0 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_HOST_INTF0>,  /* MBOX RECV */
				     <GIC_SPI INT_ATKE_WDT_IRQ IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_HOST_INTF0>, /* ATKE Watchdog */
				     <GIC_SPI INT_WFI IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_HOST_INTF0>, /* WFI */
				     <GIC_SPI INT_AMC_ERR IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_HOST_INTF0>, /* AMC ERR IRQ */
				     <GIC_SPI INT_ADSP_ACTMON IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_HOST_INTF0>, /* ADSP ACTMON IRQ */
				     <GIC_SPI INT_AMISC_MBOX_EMPTY0 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>, /* ADSP MBOX SEND */
				     <GIC_SPI INT_AMISC_MBOX_FULL1 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>, /* ADSP MBOX RECV */
				     <GIC_SPI INT_AMISC_MBOX_FULL2 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>, /* ADSP FIQ HANDLER */
				     <GIC_SPI INT_ATKE_TMR0 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>, /* ATKE TIMER 0 */
				     <GIC_SPI INT_ATKE_TMR1 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>, /* ATKE TIMER 1 */
				     <GIC_SPI INT_ATKE_TMR2 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>, /* ATKE TIMER 2 */
				     <GIC_SPI INT_SHSP2APE_DB IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>; /* SHSP2APE */
			clocks = <&bpmp_clks TEGRA194_CLK_APE>,
				<&bpmp_clks TEGRA194_CLK_APB2APE>,
				<&bpmp_clks TEGRA194_CLK_ADSPNEON>,
				<&bpmp_clks TEGRA194_CLK_ADSP>,
				<&bpmp_clks TEGRA194_CLK_ACLK>;
			clock-names = "adsp.ape", "adsp.apb2ape", "adspneon",
					"adsp", "aclk";
			resets = <&bpmp_resets TEGRA194_RESET_ADSP_ALL>;
			reset-names = "adspall";
			iommus = <&smmu TEGRA_SID_APE>;
			dma-mask = <0x0 0x5e000000>;
			iommu-resv-regions = <0x0 0x0 0x0 0x40000000 0x0 0x60000000 0xffffffff 0xffffffff>;
			iommu-group-id = <TEGRA_IOMMU_GROUP_APE>;
			status = "disabled";
		};

		adma: adma@2930000 {
			compatible = "nvidia,tegra194-adma";
			interrupt-parent = <&tegra_agic>;
			reg = <0x0 0x02930000 0x0 0x50000>,	/* ADMA Reg */
			      <0x0 0x029f0000 0x0 0x10>;	/* HSP SS */
			clocks = <&bpmp_clks TEGRA194_CLK_AHUB>;
			clock-names = "d_audio";
			interrupts =  <GIC_SPI INT_ADMA_EOT0 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT1 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT2 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT3 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT4 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT5 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT6 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT7 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT8 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT9 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT10 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT11 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT12 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT13 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT14 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT15 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT16 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT17 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT18 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT19 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT20 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT21 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT22 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT23 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT24 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT25 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT26 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT27 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT28 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT29 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT30 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>,
					  <GIC_SPI INT_ADMA_EOT31 IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>;
			#dma-cells = <1>;
			status = "disabled";
		};

		tegra_axbar: ahub {
			compatible = "nvidia,tegra186-axbar";
			wakeup-disable;
			reg = <0x0 0x02900800 0x0 0x800>;
			clocks = <&bpmp_clks TEGRA194_CLK_AHUB>,
				 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
				 <&bpmp_clks TEGRA194_CLK_APB2APE>,
				 <&bpmp_clks TEGRA194_CLK_APE>;
			clock-names = "ahub", "parent", "apb2ape", "xbar.ape";
			assigned-clocks = <&bpmp_clks TEGRA194_CLK_AHUB>;
			assigned-clock-parents =
				<&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;
			assigned-clock-rates = <81600000>;
			status = "disabled";

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			tegra_admaif: admaif@290f000 {
				compatible = "nvidia,tegra186-admaif";
				reg = <0x0 0x290f000 0x0 0x1000>;
				clocks = <&bpmp_clks TEGRA194_CLK_AHUB>;
				clock-names = "ahub";
				dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>,
					<&adma 3>, <&adma 3>, <&adma 4>, <&adma 4>,
					<&adma 5>, <&adma 5>, <&adma 6>, <&adma 6>,
					<&adma 7>, <&adma 7>, <&adma 8>, <&adma 8>,
					<&adma 9>, <&adma 9>, <&adma 10>, <&adma 10>,
					<&adma 11>, <&adma 11>, <&adma 12>, <&adma 12>,
					<&adma 13>, <&adma 13>, <&adma 14>, <&adma 14>,
					<&adma 15>, <&adma 15>, <&adma 16>, <&adma 16>,
					<&adma 17>, <&adma 17>, <&adma 18>, <&adma 18>,
					<&adma 19>, <&adma 19>, <&adma 20>, <&adma 20>;
				dma-names = "rx1", "tx1", "rx2", "tx2", "rx3", "tx3",
					"rx4", "tx4", "rx5", "tx5", "rx6", "tx6",
					"rx7", "tx7", "rx8", "tx8", "rx9", "tx9",
					"rx10", "tx10", "rx11", "tx11", "rx12", "tx12",
					"rx13", "tx13",	"rx14", "tx14", "rx15", "tx15",
					"rx16", "tx16",	"rx17", "tx17", "rx18", "tx18",
					"rx19", "tx19",	"rx20", "tx20";
				status = "disabled";
			};

			tegra_sfc1: sfc@2902000 {
				compatible = "nvidia,tegra210-sfc";
				reg = <0x0 0x2902000 0x0 0x200>;
				nvidia,ahub-sfc-id = <0>;
				status = "disabled";
			};

			tegra_sfc2: sfc@2902200 {
				compatible = "nvidia,tegra210-sfc";
				reg = <0x0 0x2902200 0x0 0x200>;
				nvidia,ahub-sfc-id = <1>;
				status = "disabled";
			};

			tegra_sfc3: sfc@2902400 {
				compatible = "nvidia,tegra210-sfc";
				reg = <0x0 0x2902400 0x0 0x200>;
				nvidia,ahub-sfc-id = <2>;
				status = "disabled";
			};

			tegra_sfc4: sfc@2902600 {
				compatible = "nvidia,tegra210-sfc";
				reg = <0x0 0x2902600 0x0 0x200>;
				nvidia,ahub-sfc-id = <3>;
				status = "disabled";
			};

			tegra_spkprot: spkprot@2908c00 {
				compatible = "nvidia,tegra210-spkprot";
				reg = <0x0 0x2908c00 0x0 0x400>;
				nvidia,ahub-spkprot-id = <0>;
				status = "disabled";
			};

			tegra_amixer: amixer@290bb00 {
				compatible = "nvidia,tegra210-amixer";
				reg = <0x0 0x290bb00 0x0 0x800>;
				nvidia,ahub-amixer-id = <0>;
				status = "disabled";
			};

			tegra_i2s1: i2s@2901000 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x0 0x2901000 0x0 0x100>;
				nvidia,ahub-i2s-id = <0>;
				clocks = <&bpmp_clks TEGRA194_CLK_I2S1>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
					 <&bpmp_clks TEGRA194_CLK_I2S1_SYNC_INPUT>,
					 <&bpmp_clks TEGRA194_CLK_SYNC_I2S1>,
					 <&bpmp_clks TEGRA194_CLK_I2S1_SYNC_INPUT>;
				clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
					      "audio_sync", "clk_sync_input";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_I2S1>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <1536000>;
				fsync-width = <31>;
				status = "disabled";
			};

			tegra_i2s2: i2s@2901100 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x0 0x2901100 0x0 0x100>;
				nvidia,ahub-i2s-id = <1>;
				clocks = <&bpmp_clks TEGRA194_CLK_I2S2>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
					 <&bpmp_clks TEGRA194_CLK_I2S2_SYNC_INPUT>,
					 <&bpmp_clks TEGRA194_CLK_SYNC_I2S2>,
					 <&bpmp_clks TEGRA194_CLK_I2S2_SYNC_INPUT>;
				clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
					      "audio_sync", "clk_sync_input";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_I2S2>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <1536000>;
				fsync-width = <31>;
				status = "disabled";
			};

			tegra_i2s3: i2s@2901200 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x0 0x2901200 0x0 0x100>;
				nvidia,ahub-i2s-id = <2>;
				clocks = <&bpmp_clks TEGRA194_CLK_I2S3>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
					 <&bpmp_clks TEGRA194_CLK_I2S3_SYNC_INPUT>,
					 <&bpmp_clks TEGRA194_CLK_SYNC_I2S3>,
					 <&bpmp_clks TEGRA194_CLK_I2S3_SYNC_INPUT>;
				clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
					      "audio_sync", "clk_sync_input";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_I2S3>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <1536000>;
				fsync-width = <31>;
				status = "disabled";
			};

			tegra_i2s4: i2s@2901300 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x0 0x2901300 0x0 0x100>;
				nvidia,ahub-i2s-id = <3>;
				clocks = <&bpmp_clks TEGRA194_CLK_I2S4>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
					 <&bpmp_clks TEGRA194_CLK_I2S4_SYNC_INPUT>,
					 <&bpmp_clks TEGRA194_CLK_SYNC_I2S4>,
					 <&bpmp_clks TEGRA194_CLK_I2S4_SYNC_INPUT>;
				clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
					      "audio_sync", "clk_sync_input";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_I2S4>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <1536000>;
				fsync-width = <31>;
				status = "disabled";
			};

			tegra_i2s5: i2s@2901400 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x0 0x2901400 0x0 0x100>;
				nvidia,ahub-i2s-id = <4>;
				clocks = <&bpmp_clks TEGRA194_CLK_I2S5>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
					 <&bpmp_clks TEGRA194_CLK_I2S5_SYNC_INPUT>,
					 <&bpmp_clks TEGRA194_CLK_SYNC_I2S5>,
					 <&bpmp_clks TEGRA194_CLK_I2S5_SYNC_INPUT>;
				clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
					      "audio_sync", "clk_sync_input";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_I2S5>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <1536000>;
				fsync-width = <31>;
				status = "disabled";
			};

			tegra_i2s6: i2s@2901500 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x0 0x2901500 0x0 0x100>;
				nvidia,ahub-i2s-id = <5>;
				clocks = <&bpmp_clks TEGRA194_CLK_I2S6>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
					 <&bpmp_clks TEGRA194_CLK_I2S6_SYNC_INPUT>,
					 <&bpmp_clks TEGRA194_CLK_SYNC_I2S6>,
					 <&bpmp_clks TEGRA194_CLK_I2S6_SYNC_INPUT>;
				clock-names = "i2s", "i2s_clk_parent", "ext_audio_sync",
					      "audio_sync", "clk_sync_input";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_I2S6>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <1536000>;
				fsync-width = <31>;
				status = "disabled";
			};

			tegra_amx1: amx@2903000 {
				compatible = "nvidia,tegra194-amx";
				reg = <0x0 0x2903000 0x0 0x100>;
				nvidia,ahub-amx-id = <0>;
				status = "disabled";
			};

			tegra_amx2: amx@2903100 {
				compatible = "nvidia,tegra194-amx";
				reg = <0x0 0x2903100 0x0 0x100>;
				nvidia,ahub-amx-id = <1>;
				status = "disabled";
			};

			tegra_amx3: amx@2903200 {
				compatible = "nvidia,tegra194-amx";
				reg = <0x0 0x2903200 0x0 0x100>;
				nvidia,ahub-amx-id = <2>;
				status = "disabled";
			};

			tegra_amx4: amx@2903300 {
				compatible = "nvidia,tegra194-amx";
				reg = <0x0 0x2903300 0x0 0x100>;
				nvidia,ahub-amx-id = <3>;
				status = "disabled";
			};

			tegra_adx1: adx@2903800 {
				compatible = "nvidia,tegra210-adx";
				reg = <0x0 0x2903800 0x0 0x100>;
				nvidia,ahub-adx-id = <0>;
				status = "disabled";
			};

			tegra_adx2: adx@2903900 {
				compatible = "nvidia,tegra210-adx";
				reg = <0x0 0x2903900 0x0 0x100>;
				nvidia,ahub-adx-id = <1>;
				status = "disabled";
			};

			tegra_adx3: adx@2903a00 {
				compatible = "nvidia,tegra210-adx";
				reg = <0x0 0x2903a00 0x0 0x100>;
				nvidia,ahub-adx-id = <2>;
				status = "disabled";
			};

			tegra_adx4: adx@2903b00 {
				compatible = "nvidia,tegra210-adx";
				reg = <0x0 0x2903b00 0x0 0x100>;
				nvidia,ahub-adx-id = <3>;
				status = "disabled";
			};

			tegra_dmic1: dmic@2904000 {
				compatible = "nvidia,tegra210-dmic";
				reg = <0x0 0x2904000 0x0 0x100>;
				nvidia,ahub-dmic-id = <0>;
				clocks = <&bpmp_clks TEGRA194_CLK_DMIC1>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				clock-names = "dmic", "parent";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_DMIC1>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <3072000>;
				status = "disabled";
			};

			tegra_dmic2: dmic@2904100 {
				compatible = "nvidia,tegra210-dmic";
				reg = <0x0 0x2904100 0x0 0x100>;
				nvidia,ahub-dmic-id = <1>;
				clocks = <&bpmp_clks TEGRA194_CLK_DMIC2>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				clock-names = "dmic", "parent";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_DMIC2>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <3072000>;
				status = "disabled";
			};

			tegra_dmic3: dmic@2904200 {
				compatible = "nvidia,tegra210-dmic";
				reg = <0x0 0x2904200 0x0 0x100>,
				      <0x0 0xc303000 0x0 0x1f0>;
				nvidia,ahub-dmic-id = <2>;
				clocks = <&bpmp_clks TEGRA194_CLK_DMIC3>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				clock-names = "dmic", "parent";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_DMIC3>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <3072000>;
				status = "disabled";
			};

			tegra_dmic4: dmic@2904300 {
				compatible = "nvidia,tegra210-dmic";
				reg = <0x0 0x2904300 0x0 0x100>;
				nvidia,ahub-dmic-id = <3>;
				clocks = <&bpmp_clks TEGRA194_CLK_DMIC4>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				clock-names = "dmic", "parent";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_DMIC4>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <3072000>;
				status = "disabled";
			};

			tegra_afc1: afc@2907000 {
				compatible = "nvidia,tegra186-afc";
				reg = <0x0 0x2907000 0x0 0x100>;
				nvidia,ahub-afc-id = <0>;
				status = "disabled";
			};

			tegra_afc2: afc@2907100 {
				compatible = "nvidia,tegra186-afc";
				reg = <0x0 0x2907100 0x0 0x100>;
				nvidia,ahub-afc-id = <1>;
				status = "disabled";
			};

			tegra_afc3: afc@2907200 {
				compatible = "nvidia,tegra186-afc";
				reg = <0x0 0x2907200 0x0 0x100>;
				nvidia,ahub-afc-id = <2>;
				status = "disabled";
			};

			tegra_afc4: afc@2907300 {
				compatible = "nvidia,tegra186-afc";
				reg = <0x0 0x2907300 0x0 0x100>;
				nvidia,ahub-afc-id = <3>;
				status = "disabled";
			};

			tegra_afc5: afc@2907400 {
				compatible = "nvidia,tegra186-afc";
				reg = <0x0 0x2907400 0x0 0x100>;
				nvidia,ahub-afc-id = <4>;
				status = "disabled";
			};

			tegra_afc6: afc@2907500 {
				compatible = "nvidia,tegra186-afc";
				reg = <0x0 0x2907500 0x0 0x100>;
				nvidia,ahub-afc-id = <5>;
				status = "disabled";
			};

			tegra_mvc1: mvc@290a000 {
				compatible = "nvidia,tegra210-mvc";
				reg = <0x0 0x290a000 0x0 0x200>;
				nvidia,ahub-mvc-id = <0>;
				status = "disabled";
			};

			tegra_mvc2: mvc@290a200 {
				compatible = "nvidia,tegra210-mvc";
				reg = <0x0 0x290a200 0x0 0x200>;
				nvidia,ahub-mvc-id = <1>;
				status = "disabled";
			};

			tegra_iqc1: iqc@290e000 {
				compatible = "nvidia,tegra210-iqc";
				reg = <0x0 0x290e000 0x0 0x200>;
				nvidia,ahub-iqc-id = <0>;
				clocks = <&bpmp_clks TEGRA194_CLK_IQC1>;
				clock-names = "iqc";
				status = "disabled";
			};

			tegra_asrc: asrc@2910000 {
				compatible = "nvidia,tegra186-asrc";
				reg = <0x0 0x2910000 0x0 0x2000>;
				nvidia,ahub-asrc-id = <0>;
				status = "disabled";
			};

			tegra_arad: arad@290e400 {
				compatible = "nvidia,tegra186-arad";
				reg = <0x0 0x290e400 0x0 0x400>;
				nvidia,ahub-arad-id = <0>;
				status = "disabled";
			};

			tegra_ahc: ahc@290b900 {
				compatible = "nvidia,tegra186-ahc";
				reg = <0x0 0x290b900 0x0 0x200>;
				interrupt-parent = <&tegra_agic>;
				interrupts =  <GIC_SPI INT_AHUB_ERR IRQ_TYPE_LEVEL_HIGH ROUTE_TO_HOST_INTF0>;
				status = "disabled";
			};

			tegra_ope1: ope@2908000 {
				compatible = "nvidia,tegra210-ope";
				reg = <0x0 0x2908000 0x0 0x100>,
				      <0x0 0x2908100 0x0 0x100>,
				      <0x0 0x2908200 0x0 0x200>;
				nvidia,ahub-ope-id = <0>;
				status = "disabled";
			};

			tegra_dspk1: dspk@2905000 {
				compatible = "nvidia,tegra186-dspk";
				reg = <0x0 0x2905000 0x0 0x100>;
				nvidia,ahub-dspk-id = <0>;
				clocks = <&bpmp_clks TEGRA194_CLK_DSPK1>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
					 <&bpmp_clks TEGRA194_CLK_SYNC_DSPK1>;
				clock-names = "dspk", "pll_a_out0", "sync_dspk";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_DSPK1>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <12288000>;
				status = "disabled";
			};

			tegra_dspk2: dspk@2905100 {
				compatible = "nvidia,tegra186-dspk";
				reg = <0x0 0x2905100 0x0 0x100>,
				      <0x0 0x2431000 0x0 0x1F0>;
				nvidia,ahub-dspk-id = <1>;
				clocks = <&bpmp_clks TEGRA194_CLK_DSPK2>,
					 <&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
					 <&bpmp_clks TEGRA194_CLK_SYNC_DSPK2>;
				clock-names = "dspk", "pll_a_out0", "sync_dspk";
				assigned-clocks =
					<&bpmp_clks TEGRA194_CLK_DSPK2>;
				assigned-clock-parents =
					<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>;
				assigned-clock-rates = <12288000>;
				status = "disabled";
			};
		};

		tegra_adsp_audio: adsp_audio {
			compatible = "nvidia,tegra186-adsp-audio";
			clocks = <&bpmp_clks TEGRA194_CLK_AHUB>,
				<&bpmp_clks TEGRA194_CLK_APE>,
				<&bpmp_clks TEGRA194_CLK_APB2APE>;
			clock-names = "ahub", "ape", "apb2ape";
			wakeup-disable;
			nvidia,adma_ch_start = <16>;
			nvidia,adma_ch_cnt = <16>;
			iommus = <&smmu TEGRA_SID_APE>;
			iommu-resv-regions = <0x0 0x0 0x0 0x40000000 0x0 0x60000000 0xffffffff 0xffffffff>;
			iommu-group-id = <TEGRA_IOMMU_GROUP_APE>;
			interrupt-parent = <&tegra_agic>;
			interrupts = <GIC_SPI INT_ADMA_EOT16 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT17 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT18 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT19 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT20 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT21 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT22 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT23 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT24 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT25 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT26 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT27 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT28 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT29 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT30 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>,
				     <GIC_SPI INT_ADMA_EOT31 IRQ_TYPE_LEVEL_HIGH
					ROUTE_TO_ADSP>;
			status = "disabled";
		};
	};

	hda@3510000 {
		compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
		hda,card-name = "tegra-hda-galen-t194";
		iommus = <&smmu TEGRA_SID_HDA>;
		reg = <0x0 0x3510000 0x0 0x10000>;
		clocks = <&bpmp_clks TEGRA194_CLK_PLLP_OUT0>,
			 <&bpmp_clks TEGRA194_CLK_MAUD>,
			 <&bpmp_clks TEGRA194_CLK_HDA>,
			 <&bpmp_clks TEGRA194_CLK_HDA2CODEC_2X>,
			 <&bpmp_clks TEGRA194_CLK_HDA2HDMICODEC>;
		clock-names = "pllp_out0", "maud", "hda",
				"hda2codec_2x",	"hda2hdmi";
		interrupts = <0 161 0x04>;
		status = "disabled";
	};

	eqos_ape@2990000 {
		status = "disabled";
		compatible = "nvidia,tegra18x-eqos-ape";
		wakeup-disable;
		reg = <0x0 0x02990054 0x0 0x4>, /* AMISC IDLE*/
			<0x0 0x029900c0 0x0 0x28>;  /* AMISC EAVB*/
		clocks = <&bpmp_clks TEGRA194_CLK_APE>,
			<&bpmp_clks TEGRA194_CLK_PLLA_OUT0>,
			<&bpmp_clks TEGRA194_CLK_PLLA>;
		clock-names = "eqos_ape.ape", "pll_a_out0", "pll_a";
	};
};