From f840e6cd77b1b2e0e51d6d560f536e8dd35ece5e Mon Sep 17 00:00:00 2001
From: Andrew Tridgell <andrew@tridgell.net>
Date: Sat, 27 Jul 2019 20:57:21 +1000
Subject: [PATCH] ChibiOS: added automatic reset of SPI peripherals on STM32

An electrical glitch (such as shorting the SCK and MOSI pins) can
cause the SPI peripheral on a STM32F7xx to get into a state where it
receives corrupted bytes on the bus. This detects that state by
looking for unexpected bytes on the FIFO and resetting the peripheral
using the RCC
---
 modules/ChibiOS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/modules/ChibiOS b/modules/ChibiOS
index 266646ea1e..b96e543701 160000
--- a/modules/ChibiOS
+++ b/modules/ChibiOS
@@ -1 +1 @@
-Subproject commit 266646ea1e9a9d576339556a88a444a915405e29
+Subproject commit b96e543701dd16b05e63be647f5a000cf4c7a023