From 94c0701f172064b2c5ea9525cec0b33b826d6337 Mon Sep 17 00:00:00 2001 From: Henry Wurzburg Date: Mon, 28 Mar 2022 11:37:39 -0500 Subject: [PATCH] HWDEF: add SLCAN OTG port, correct defaults.param errors --- .../AP_HAL_ChibiOS/hwdef/QioTekZealotH743/defaults.parm | 8 ++++---- libraries/AP_HAL_ChibiOS/hwdef/QioTekZealotH743/hwdef.dat | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/libraries/AP_HAL_ChibiOS/hwdef/QioTekZealotH743/defaults.parm b/libraries/AP_HAL_ChibiOS/hwdef/QioTekZealotH743/defaults.parm index fb5477cba0..65b893da7c 100644 --- a/libraries/AP_HAL_ChibiOS/hwdef/QioTekZealotH743/defaults.parm +++ b/libraries/AP_HAL_ChibiOS/hwdef/QioTekZealotH743/defaults.parm @@ -2,10 +2,10 @@ BRD_HEAT_TARG 45 # setup serial2 port defaults for ESP8266 -define HAL_SERIAL2_PROTOCOL SerialProtocol_MAVLink2 -define HAL_SERIAL2_BAUD 921600 +SERIAL2_BAUD 921600 # setup the parameter for the ADC power module +BATT_MONITOR 4 BATT_VOLT_PIN 16 BATT_CURR_PIN 17 BATT_VOLT_MULT 20.000 @@ -16,5 +16,5 @@ BATT2_VOLT_MULT 20.000 BATT2_AMP_PERVLT 17.000 # setup the parameter for the two Relays GPIO others for reserve -define RELAY1_PIN_DEFAULT 1 -define RELAY2_PIN_DEFAULT 2 \ No newline at end of file +RELAY_PIN 1 +RELAY_PIN2 2 diff --git a/libraries/AP_HAL_ChibiOS/hwdef/QioTekZealotH743/hwdef.dat b/libraries/AP_HAL_ChibiOS/hwdef/QioTekZealotH743/hwdef.dat index bed152a23b..d2470c5a1c 100644 --- a/libraries/AP_HAL_ChibiOS/hwdef/QioTekZealotH743/hwdef.dat +++ b/libraries/AP_HAL_ChibiOS/hwdef/QioTekZealotH743/hwdef.dat @@ -20,7 +20,7 @@ STM32_ST_USE_TIMER 2 FLASH_RESERVE_START_KB 128 # order of UARTs (and USB) -SERIAL_ORDER OTG1 USART1 USART2 USART3 UART4 UART7 +SERIAL_ORDER OTG1 USART1 USART2 USART3 UART4 UART7 OTG2 # now we define the pins that USB is connected on PA11 OTG_FS_DM OTG1