From 876899c48d31c6dd962f339ac4c6256d014bb553 Mon Sep 17 00:00:00 2001 From: Andrew Tridgell Date: Tue, 29 May 2018 19:51:37 +1000 Subject: [PATCH] HAL_ChibiOS: baro and FRAM working for fmuv5 --- .../AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat | 63 +++++++++++++++++-- 1 file changed, 59 insertions(+), 4 deletions(-) diff --git a/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat b/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat index ff82a86f38..c84dc7ffc4 100644 --- a/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat +++ b/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat @@ -1,7 +1,8 @@ # hw definition file for processing by chibios_hwdef.py # for FMUv3 hardware (ie. for CUAV-PixHack-v5 and Pixhawk4) -# MCU class and specific type +# MCU class and specific type. It is a F765, which is the same as F767 +# but without the TFT interface MCU STM32F7xx STM32F767xx # crystal frequency @@ -39,14 +40,68 @@ PA12 OTG_FS_DP OTG1 PA13 JTMS-SWDIO SWD PA14 JTCK-SWCLK SWD -define HAL_USE_EMPTY_STORAGE 1 +# SPI1 - internal sensors +PG11 SPI1_SCK SPI1 +PA6 SPI1_MISO SPI1 +PD7 SPI1_MOSI SPI1 + +# SPI2 - FRAM +PI1 SPI2_SCK SPI2 +PI2 SPI2_MISO SPI2 +PI3 SPI2_MOSI SPI2 + +# SPI4 - sensors2 +PE2 SPI4_SCK SPI4 +PE13 SPI4_MISO SPI4 +PE6 SPI4_MOSI SPI4 + +# SPI5 - external1 +PF7 SPI5_SCK SPI5 +PF8 SPI5_MISO SPI5 +PF9 SPI5_MOSI SPI5 + +# SPI6 - external2 +PG13 SPI6_SCK SPI6 +PG12 SPI6_MISO SPI6 +PB5 SPI6_MOSI SPI6 + +# sensor CS +PF10 MS5611_CS CS +PF2 ICM20689_CS CS +PF3 ICM20602_CS CS +PF4 BMI055_G_CS CS +PG10 BMI055_A_CS CS +PF5 FRAM_CS CS SPEED_VERYLOW + +# enable pins +PE3 VDD_3V3_SENSORS_EN OUTPUT HIGH +PF12 nVDD_5V_HIPOWER_EN OUTPUT LOW +PG4 nVDD_5V_PERIPH_EN OUTPUT LOW +PG5 VDD_5V_RC_EN OUTPUT HIGH +PG6 VDD_5V_WIFI_EN OUTPUT HIGH +PG7 VDD_3V3_SD_CARD_EN OUTPUT HIGH + +SPIDEV ms5611 SPI4 DEVID1 MS5611_CS MODE3 20*MHZ 20*MHZ +SPIDEV mpu6000 SPI1 DEVID1 ICM20689_CS MODE3 1*MHZ 1*MHZ +SPIDEV mpu60002 SPI1 DEVID2 ICM20602_CS MODE3 1*MHZ 1*MHZ +SPIDEV bmi055_g SPI1 DEVID3 BMI055_G_CS MODE3 8*MHZ 8*MHZ +SPIDEV bmi055_a SPI1 DEVID4 BMI055_A_CS MODE3 8*MHZ 8*MHZ +SPIDEV ramtron SPI2 DEVID1 FRAM_CS MODE3 8*MHZ 8*MHZ + +# enable RAMTROM parameter storage define HAL_STORAGE_SIZE 16384 +define HAL_WITH_RAMTRON 1 + +define STORAGE_FLASH_PAGE 7 + +define HAL_BARO_DEFAULT HAL_BARO_MS5611_SPI +define HAL_INS_DEFAULT HAL_INS_MPU60XX_SPI define HAL_COMPASS_DEFAULT HAL_COMPASS_NONE -define HAL_INS_DEFAULT HAL_INS_NONE -define HAL_BARO_DEFAULT HAL_BARO_NONE define CH_DBG_ENABLE_ASSERTS TRUE define CH_DBG_ENABLE_CHECKS TRUE define CH_DBG_SYSTEM_STATE_CHECK TRUE define CH_DBG_ENABLE_STACK_CHECK TRUE + +define HAL_SPI_CHECK_CLOCK_FREQ 1