From 7c09a1781bb954a676a107304b95e4cbe88f507b Mon Sep 17 00:00:00 2001
From: Andrew Tridgell <andrew@tridgell.net>
Date: Tue, 29 May 2018 16:07:36 +1000
Subject: [PATCH] HAL_ChibiOS: started on fmuv5

---
 .../AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat      | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat

diff --git a/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat b/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat
new file mode 100644
index 0000000000..ff82a86f38
--- /dev/null
+++ b/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat
@@ -0,0 +1,52 @@
+# hw definition file for processing by chibios_hwdef.py
+# for FMUv3 hardware (ie. for CUAV-PixHack-v5 and Pixhawk4)
+
+# MCU class and specific type
+MCU STM32F7xx STM32F767xx
+
+# crystal frequency
+OSCILLATOR_HZ 16000000
+
+define STM32_LSECLK 32768U
+define STM32_LSEDRV (3U << 3U)
+define STM32_PLLSRC STM32_PLLSRC_HSE
+define STM32_PLLM_VALUE 8
+define STM32_PLLN_VALUE 216
+define STM32_PLLP_VALUE 2
+define STM32_PLLQ_VALUE 9
+
+define CONFIG_HAL_BOARD_SUBTYPE HAL_BOARD_SUBTYPE_CHIBIOS_FMUV5
+
+# board ID for firmware load
+APJ_BOARD_ID 50
+
+FLASH_RESERVE_START_KB 32
+
+# board voltage
+STM32_VDD 330U
+
+# flash size
+FLASH_SIZE_KB 2048
+
+# order of UARTs (and USB)
+UART_ORDER OTG1
+
+# now we define the pins that USB is connected on
+PA11 OTG_FS_DM OTG1
+PA12 OTG_FS_DP OTG1
+
+# these are the pins for SWD debugging with a STlinkv2 or black-magic probe
+PA13 JTMS-SWDIO SWD
+PA14 JTCK-SWCLK SWD
+
+define HAL_USE_EMPTY_STORAGE 1
+define HAL_STORAGE_SIZE 16384
+
+define HAL_COMPASS_DEFAULT HAL_COMPASS_NONE
+define HAL_INS_DEFAULT HAL_INS_NONE
+define HAL_BARO_DEFAULT HAL_BARO_NONE
+
+define CH_DBG_ENABLE_ASSERTS TRUE
+define CH_DBG_ENABLE_CHECKS TRUE
+define CH_DBG_SYSTEM_STATE_CHECK TRUE
+define CH_DBG_ENABLE_STACK_CHECK TRUE