From 56ce3f057db0d23e382663cb09194d3a01dfa89b Mon Sep 17 00:00:00 2001
From: Andrew Tridgell <andrew@tridgell.net>
Date: Fri, 1 Jun 2018 21:22:11 +1000
Subject: [PATCH] HAL_ChibiOS: added DRDY and SDMMC pins for FMUv5

---
 .../AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat      | 23 ++++++++++++++-----
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat b/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat
index 2c5bc3bdb3..10861e6740 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat
+++ b/libraries/AP_HAL_ChibiOS/hwdef/fmuv5/hwdef.dat
@@ -107,6 +107,16 @@ PG5  VDD_5V_RC_EN OUTPUT HIGH
 PG6  VDD_5V_WIFI_EN OUTPUT HIGH
 PG7  VDD_3V3_SD_CARD_EN OUTPUT HIGH
 
+# drdy pins
+PE7  DRDY8_NC INPUT
+PB4  DRDY1_ICM20689 INPUT
+PB14 DRDY2_BMI055_GYRO INPUT
+PB15 DRDY3_BMI055_ACC INPUT
+PC5  DRDY4_ICM20602 INPUT
+PC13 DRDY5_BMI055_GYRO INPUT
+PD10 DRDY6_BMI055_ACC INPUT
+PD15 DRDY7_EXTERNAL1 INPUT
+
 # UARTs
 
 # USART2 is telem1
@@ -216,11 +226,12 @@ SPIDEV bmi055_a       SPI1 DEVID4  BMI055_A_CS  MODE3  8*MHZ  8*MHZ
 SPIDEV ramtron        SPI2 DEVID1  FRAM_CS      MODE3  8*MHZ  8*MHZ 
 
 # microSD support
-#PC8 SDMMC_D0 SDMMC1
-#PC9 SDMMC_D1 SDMMC1
-#PC10 SDMMC_D2 SDMMC1
-#PC11 SDMMC_D3 SDMMC1
-#PC12 SDMMC_CK SDMMC1
+PC8 SDMMC_D0 SDMMC1
+PC9 SDMMC_D1 SDMMC1
+PC10 SDMMC_D2 SDMMC1
+PC11 SDMMC_D3 SDMMC1
+PC12 SDMMC_CK SDMMC1
+PD2 SDMMC_CMD SDMMC1
 
 # enable RAMTROM parameter storage
 define HAL_STORAGE_SIZE 16384
@@ -232,7 +243,7 @@ define HAL_BARO_DEFAULT HAL_BARO_MS5611_SPI
 
 define HAL_COMPASS_DEFAULT HAL_COMPASS_NONE
 
-DMA_PRIORITY UART8* ADC* SPI* TIM*
+DMA_PRIORITY SDMMC* UART8* ADC* SPI* TIM*
 
 define CH_DBG_ENABLE_ASSERTS TRUE
 define CH_DBG_ENABLE_CHECKS TRUE